package CommSub

import chisel3._
import chisel3.util._
import common._
import common.axi._

class HBM_DRIVER(WITH_RAMA: Boolean=true) extends Module{

	def getTCL() = {
		val s1 = "\ncreate_ip -name hbm -vendor xilinx.com -library ip -version 1.0 -module_name HBMBlackBox\n"
		val s2 = "set_property -dict [list CONFIG.USER_HBM_DENSITY {8GB}  CONFIG.USER_HBM_STACK {2}  CONFIG.USER_MEMORY_DISPLAY {8192}  CONFIG.USER_SWITCH_ENABLE_01 {TRUE}  CONFIG.USER_HBM_CP_1 {6}  CONFIG.USER_HBM_RES_1 {10}  CONFIG.USER_HBM_LOCK_REF_DLY_1 {31}  CONFIG.USER_HBM_LOCK_FB_DLY_1 {31}  CONFIG.USER_HBM_FBDIV_1 {36}  CONFIG.USER_HBM_HEX_CP_RES_1 {0x0000A600}  CONFIG.USER_HBM_HEX_LOCK_FB_REF_DLY_1 {0x00001f1f}  CONFIG.USER_HBM_HEX_FBDIV_CLKOUTDIV_1 {0x00000902}  CONFIG.USER_MC0_TRAFFIC_OPTION {Linear}  CONFIG.USER_MC1_TRAFFIC_OPTION {Linear}  CONFIG.USER_MC2_TRAFFIC_OPTION {Linear}  CONFIG.USER_MC3_TRAFFIC_OPTION {Linear}  CONFIG.USER_MC4_TRAFFIC_OPTION {Linear}  CONFIG.USER_MC5_TRAFFIC_OPTION {Linear}  CONFIG.USER_MC6_TRAFFIC_OPTION {Linear}  CONFIG.USER_MC7_TRAFFIC_OPTION {Linear}  CONFIG.USER_MC8_TRAFFIC_OPTION {Linear}  CONFIG.USER_MC9_TRAFFIC_OPTION {Linear}  CONFIG.USER_MC10_TRAFFIC_OPTION {Linear}  CONFIG.USER_MC11_TRAFFIC_OPTION {Linear}  CONFIG.USER_MC12_TRAFFIC_OPTION {Linear}  CONFIG.USER_MC13_TRAFFIC_OPTION {Linear}  CONFIG.USER_MC14_TRAFFIC_OPTION {Linear}  CONFIG.USER_MC15_TRAFFIC_OPTION {Linear}  CONFIG.USER_CLK_SEL_LIST1 {AXI_23_ACLK}  CONFIG.USER_MC_ENABLE_08 {TRUE}  CONFIG.USER_MC_ENABLE_09 {TRUE}  CONFIG.USER_MC_ENABLE_10 {TRUE}  CONFIG.USER_MC_ENABLE_11 {TRUE}  CONFIG.USER_MC_ENABLE_12 {TRUE}  CONFIG.USER_MC_ENABLE_13 {TRUE}  CONFIG.USER_MC_ENABLE_14 {TRUE}  CONFIG.USER_MC_ENABLE_15 {TRUE}  CONFIG.USER_MC_ENABLE_APB_01 {TRUE}  CONFIG.USER_MC0_LOOKAHEAD_SBRF {true}  CONFIG.USER_MC1_LOOKAHEAD_SBRF {true}  CONFIG.USER_MC2_LOOKAHEAD_SBRF {true}  CONFIG.USER_MC3_LOOKAHEAD_SBRF {true}  CONFIG.USER_MC4_LOOKAHEAD_SBRF {true}  CONFIG.USER_MC5_LOOKAHEAD_SBRF {true}  CONFIG.USER_MC6_LOOKAHEAD_SBRF {true}  CONFIG.USER_MC7_LOOKAHEAD_SBRF {true}  CONFIG.USER_MC8_LOOKAHEAD_SBRF {true}  CONFIG.USER_MC9_LOOKAHEAD_SBRF {true}  CONFIG.USER_MC10_LOOKAHEAD_SBRF {true}  CONFIG.USER_MC11_LOOKAHEAD_SBRF {true}  CONFIG.USER_MC12_LOOKAHEAD_SBRF {true}  CONFIG.USER_MC13_LOOKAHEAD_SBRF {true}  CONFIG.USER_MC14_LOOKAHEAD_SBRF {true}  CONFIG.USER_MC15_LOOKAHEAD_SBRF {true}  CONFIG.USER_MC0_EN_SBREF {true}  CONFIG.USER_MC1_EN_SBREF {true}  CONFIG.USER_MC2_EN_SBREF {true}  CONFIG.USER_MC3_EN_SBREF {true}  CONFIG.USER_MC4_EN_SBREF {true}  CONFIG.USER_MC5_EN_SBREF {true}  CONFIG.USER_MC6_EN_SBREF {true}  CONFIG.USER_MC7_EN_SBREF {true}  CONFIG.USER_MC8_EN_SBREF {true}  CONFIG.USER_MC9_EN_SBREF {true}  CONFIG.USER_MC10_EN_SBREF {true}  CONFIG.USER_MC11_EN_SBREF {true}  CONFIG.USER_MC12_EN_SBREF {true}  CONFIG.USER_MC13_EN_SBREF {true}  CONFIG.USER_MC14_EN_SBREF {true}  CONFIG.USER_MC15_EN_SBREF {true}  CONFIG.USER_PHY_ENABLE_08 {TRUE}  CONFIG.USER_PHY_ENABLE_09 {TRUE}  CONFIG.USER_PHY_ENABLE_10 {TRUE}  CONFIG.USER_PHY_ENABLE_11 {TRUE}  CONFIG.USER_PHY_ENABLE_12 {TRUE}  CONFIG.USER_PHY_ENABLE_13 {TRUE}  CONFIG.USER_PHY_ENABLE_14 {TRUE}  CONFIG.USER_PHY_ENABLE_15 {TRUE}] [get_ips HBMBlackBox]\n"
		val s3 = "update_compile_order -fileset sources_1\n"
		println("\nThe tcl below is used to generate HBM IP:\n" + s1 + s2 + s3)

		if (WITH_RAMA) {
			// RAMA tcl
			val s1 = "\ncreate_ip -name rama -vendor xilinx.com -library ip -version 1.1 -module_name RAMABlackBox\n"
			val s2 = f"set_property -dict [list CONFIG.ID_WIDTH {6} CONFIG.ADDR_WIDTH {33}] [get_ips RAMABlackBox]\n"
			val s3 = "update_compile_order -fileset sources_1\n"
			println("\nThe tcl below is used to generate RAMA IP:\n" + s1 + s2 + s3)
		}
	}

	val io = IO(new Bundle{
		val hbm_clk			= Output(Clock())
		val hbm_rstn 		= Output(UInt(1.W))
		val axi_hbm 		= Vec(32,Flipped(new AXI(34, 256, 6, 0, 4)))
	})

	// AXI bus connected as HBM ports
	val axi_hbm_port = Wire(Vec(32, Flipped(new AXI(34, 256, 6, 0, 4))))

	// Optional RAMA
	var i = 0
	for (i <- 0 until 32) {
		val rama = if (WITH_RAMA) {Some(withClockAndReset(io.hbm_clk, !io.hbm_rstn){Module(new RAMA)})} else None
		if (WITH_RAMA) {
			io.axi_hbm(i) <> rama.get.io.s_axi
			rama.get.io.m_axi <> axi_hbm_port(i)
		} else {
			io.axi_hbm(i) <> axi_hbm_port(i)
		}
	}

	// HBM part

	val mmcmGlbl = Module(new MMCME4_ADV_Wrapper(
		CLKFBOUT_MULT_F 		= 12,
		MMCM_DIVCLK_DIVIDE		= 1,
		MMCM_CLKOUT0_DIVIDE_F	= 12,
		MMCM_CLKOUT1_DIVIDE_F	= 12,
		MMCM_CLKOUT2_DIVIDE_F	= 12,
		MMCM_CLKOUT3_DIVIDE_F	= 12,
		MMCM_CLKOUT4_DIVIDE_F	= 12,
		MMCM_CLKOUT5_DIVIDE_F	= 12,
		MMCM_CLKIN1_PERIOD 		= 10
	))

	mmcmGlbl.io.CLKIN1	:= clock
	mmcmGlbl.io.RST		:= reset.asUInt()
	
	val apb0Pclk	= BUFG(IBUF(BUFG(mmcmGlbl.io.CLKOUT0).asBool).asClock)
	val axiAclkIn0	= BUFG(mmcmGlbl.io.CLKOUT1)
	val hbmRefClk0	= BUFG(mmcmGlbl.io.CLKOUT2)
	val apb1Pclk	= BUFG(IBUF(BUFG(mmcmGlbl.io.CLKOUT3).asBool).asClock)
	val axiAclkIn1	= BUFG(mmcmGlbl.io.CLKOUT4)
	val hbmRefClk1	= BUFG(mmcmGlbl.io.CLKOUT5)
	val glblLocked	= mmcmGlbl.io.LOCKED

	val mmcmAxi = Module(new MMCME4_ADV_Wrapper(
		CLKFBOUT_MULT_F 		= 18,
		MMCM_DIVCLK_DIVIDE		= 2,
		MMCM_CLKOUT0_DIVIDE_F	= 2,
		MMCM_CLKOUT1_DIVIDE_F	= 2,
		MMCM_CLKOUT2_DIVIDE_F	= 2,
		MMCM_CLKOUT3_DIVIDE_F	= 2,
		MMCM_CLKOUT4_DIVIDE_F	= 2,
		MMCM_CLKOUT5_DIVIDE_F	= 2,
		MMCM_CLKOUT6_DIVIDE_F	= 2,
		MMCM_CLKIN1_PERIOD 		= 10
	))

	mmcmAxi.io.CLKIN1	:= axiAclkIn0
	mmcmAxi.io.RST		:= !glblLocked

	val axiAclk 	= BUFG(mmcmAxi.io.CLKOUT0)
	val axiLocked	= mmcmAxi.io.LOCKED

	io.hbm_clk	:= axiAclk 

	val instHbm = Module(new HBMBlackBox)

	val apb_complete_0 = withClock(apb0Pclk) {ShiftRegister(instHbm.io.apb_complete_0, 2)}
	val apb_complete_1 = withClock(apb1Pclk) {ShiftRegister(instHbm.io.apb_complete_1, 2)}

	io.hbm_rstn := withClock(axiAclk) {(RegNext(axiLocked.asBool)
		&& apb_complete_0.asBool 
		&& apb_complete_1.asBool
	)}

	// Global clocks
	instHbm.io.HBM_REF_CLK_0	:= hbmRefClk0
	instHbm.io.HBM_REF_CLK_1	:= hbmRefClk1
	
	// Anonymous functions are used to split the whole init method,
	// thus to prevent Java's "method too large" error.
	val hbmInit1 = (
		instHbm : HBMBlackBox,
		axi_hbm_port: Vec[AXI],
		axiAclk : Clock,
		axiLocked : UInt
	) => {
		// AXI Channels
		instHbm.io.AXI_00_ACLK		<> axiAclk
		instHbm.io.AXI_00_ARESET_N	<> axiLocked
		instHbm.io.AXI_00_ARADDR   	<> axi_hbm_port(0).ar.bits.addr
		instHbm.io.AXI_00_ARBURST  	<> axi_hbm_port(0).ar.bits.burst
		instHbm.io.AXI_00_ARID     	<> axi_hbm_port(0).ar.bits.id
		instHbm.io.AXI_00_ARLEN    	<> axi_hbm_port(0).ar.bits.len
		instHbm.io.AXI_00_ARSIZE   	<> axi_hbm_port(0).ar.bits.size
		instHbm.io.AXI_00_ARVALID  	<> axi_hbm_port(0).ar.valid
		instHbm.io.AXI_00_ARREADY  	<> axi_hbm_port(0).ar.ready
		instHbm.io.AXI_00_AWADDR   	<> axi_hbm_port(0).aw.bits.addr
		instHbm.io.AXI_00_AWBURST  	<> axi_hbm_port(0).aw.bits.burst
		instHbm.io.AXI_00_AWID     	<> axi_hbm_port(0).aw.bits.id
		instHbm.io.AXI_00_AWLEN    	<> axi_hbm_port(0).aw.bits.len
		instHbm.io.AXI_00_AWSIZE   	<> axi_hbm_port(0).aw.bits.size
		instHbm.io.AXI_00_AWVALID  	<> axi_hbm_port(0).aw.valid
		instHbm.io.AXI_00_AWREADY  	<> axi_hbm_port(0).aw.ready
		instHbm.io.AXI_00_WDATA    	<> axi_hbm_port(0).w.bits.data
		instHbm.io.AXI_00_WLAST    	<> axi_hbm_port(0).w.bits.last
		instHbm.io.AXI_00_WSTRB    	<> axi_hbm_port(0).w.bits.strb
		instHbm.io.AXI_00_WVALID   	<> axi_hbm_port(0).w.valid
		instHbm.io.AXI_00_WREADY   	<> axi_hbm_port(0).w.ready
		instHbm.io.AXI_00_RDATA    	<> axi_hbm_port(0).r.bits.data
		instHbm.io.AXI_00_RID      	<> axi_hbm_port(0).r.bits.id
		instHbm.io.AXI_00_RLAST    	<> axi_hbm_port(0).r.bits.last
		instHbm.io.AXI_00_RRESP    	<> axi_hbm_port(0).r.bits.resp
		instHbm.io.AXI_00_RVALID   	<> axi_hbm_port(0).r.valid
		instHbm.io.AXI_00_RREADY   	<> axi_hbm_port(0).r.ready
		instHbm.io.AXI_00_BID      	<> axi_hbm_port(0).b.bits.id
		instHbm.io.AXI_00_BRESP    	<> axi_hbm_port(0).b.bits.resp
		instHbm.io.AXI_00_BVALID   	<> axi_hbm_port(0).b.valid
		instHbm.io.AXI_00_BREADY   	<> axi_hbm_port(0).b.ready
		instHbm.io.AXI_00_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_00_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_01_ACLK		<> axiAclk
		instHbm.io.AXI_01_ARESET_N	<> axiLocked
		instHbm.io.AXI_01_ARADDR   	<> axi_hbm_port(1).ar.bits.addr
		instHbm.io.AXI_01_ARBURST  	<> axi_hbm_port(1).ar.bits.burst
		instHbm.io.AXI_01_ARID     	<> axi_hbm_port(1).ar.bits.id
		instHbm.io.AXI_01_ARLEN    	<> axi_hbm_port(1).ar.bits.len
		instHbm.io.AXI_01_ARSIZE   	<> axi_hbm_port(1).ar.bits.size
		instHbm.io.AXI_01_ARVALID  	<> axi_hbm_port(1).ar.valid
		instHbm.io.AXI_01_ARREADY  	<> axi_hbm_port(1).ar.ready
		instHbm.io.AXI_01_AWADDR   	<> axi_hbm_port(1).aw.bits.addr
		instHbm.io.AXI_01_AWBURST  	<> axi_hbm_port(1).aw.bits.burst
		instHbm.io.AXI_01_AWID     	<> axi_hbm_port(1).aw.bits.id
		instHbm.io.AXI_01_AWLEN    	<> axi_hbm_port(1).aw.bits.len
		instHbm.io.AXI_01_AWSIZE   	<> axi_hbm_port(1).aw.bits.size
		instHbm.io.AXI_01_AWVALID  	<> axi_hbm_port(1).aw.valid
		instHbm.io.AXI_01_AWREADY  	<> axi_hbm_port(1).aw.ready
		instHbm.io.AXI_01_WDATA    	<> axi_hbm_port(1).w.bits.data
		instHbm.io.AXI_01_WLAST    	<> axi_hbm_port(1).w.bits.last
		instHbm.io.AXI_01_WSTRB    	<> axi_hbm_port(1).w.bits.strb
		instHbm.io.AXI_01_WVALID   	<> axi_hbm_port(1).w.valid
		instHbm.io.AXI_01_WREADY   	<> axi_hbm_port(1).w.ready
		instHbm.io.AXI_01_RDATA    	<> axi_hbm_port(1).r.bits.data
		instHbm.io.AXI_01_RID      	<> axi_hbm_port(1).r.bits.id
		instHbm.io.AXI_01_RLAST    	<> axi_hbm_port(1).r.bits.last
		instHbm.io.AXI_01_RRESP    	<> axi_hbm_port(1).r.bits.resp
		instHbm.io.AXI_01_RVALID   	<> axi_hbm_port(1).r.valid
		instHbm.io.AXI_01_RREADY   	<> axi_hbm_port(1).r.ready
		instHbm.io.AXI_01_BID      	<> axi_hbm_port(1).b.bits.id
		instHbm.io.AXI_01_BRESP    	<> axi_hbm_port(1).b.bits.resp
		instHbm.io.AXI_01_BVALID   	<> axi_hbm_port(1).b.valid
		instHbm.io.AXI_01_BREADY   	<> axi_hbm_port(1).b.ready
		instHbm.io.AXI_01_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_01_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_02_ACLK		<> axiAclk
		instHbm.io.AXI_02_ARESET_N	<> axiLocked
		instHbm.io.AXI_02_ARADDR   	<> axi_hbm_port(2).ar.bits.addr
		instHbm.io.AXI_02_ARBURST  	<> axi_hbm_port(2).ar.bits.burst
		instHbm.io.AXI_02_ARID     	<> axi_hbm_port(2).ar.bits.id
		instHbm.io.AXI_02_ARLEN    	<> axi_hbm_port(2).ar.bits.len
		instHbm.io.AXI_02_ARSIZE   	<> axi_hbm_port(2).ar.bits.size
		instHbm.io.AXI_02_ARVALID  	<> axi_hbm_port(2).ar.valid
		instHbm.io.AXI_02_ARREADY  	<> axi_hbm_port(2).ar.ready
		instHbm.io.AXI_02_AWADDR   	<> axi_hbm_port(2).aw.bits.addr
		instHbm.io.AXI_02_AWBURST  	<> axi_hbm_port(2).aw.bits.burst
		instHbm.io.AXI_02_AWID     	<> axi_hbm_port(2).aw.bits.id
		instHbm.io.AXI_02_AWLEN    	<> axi_hbm_port(2).aw.bits.len
		instHbm.io.AXI_02_AWSIZE   	<> axi_hbm_port(2).aw.bits.size
		instHbm.io.AXI_02_AWVALID  	<> axi_hbm_port(2).aw.valid
		instHbm.io.AXI_02_AWREADY  	<> axi_hbm_port(2).aw.ready
		instHbm.io.AXI_02_WDATA    	<> axi_hbm_port(2).w.bits.data
		instHbm.io.AXI_02_WLAST    	<> axi_hbm_port(2).w.bits.last
		instHbm.io.AXI_02_WSTRB    	<> axi_hbm_port(2).w.bits.strb
		instHbm.io.AXI_02_WVALID   	<> axi_hbm_port(2).w.valid
		instHbm.io.AXI_02_WREADY   	<> axi_hbm_port(2).w.ready
		instHbm.io.AXI_02_RDATA    	<> axi_hbm_port(2).r.bits.data
		instHbm.io.AXI_02_RID      	<> axi_hbm_port(2).r.bits.id
		instHbm.io.AXI_02_RLAST    	<> axi_hbm_port(2).r.bits.last
		instHbm.io.AXI_02_RRESP    	<> axi_hbm_port(2).r.bits.resp
		instHbm.io.AXI_02_RVALID   	<> axi_hbm_port(2).r.valid
		instHbm.io.AXI_02_RREADY   	<> axi_hbm_port(2).r.ready
		instHbm.io.AXI_02_BID      	<> axi_hbm_port(2).b.bits.id
		instHbm.io.AXI_02_BRESP    	<> axi_hbm_port(2).b.bits.resp
		instHbm.io.AXI_02_BVALID   	<> axi_hbm_port(2).b.valid
		instHbm.io.AXI_02_BREADY   	<> axi_hbm_port(2).b.ready
		instHbm.io.AXI_02_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_02_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_03_ACLK		<> axiAclk
		instHbm.io.AXI_03_ARESET_N	<> axiLocked
		instHbm.io.AXI_03_ARADDR   	<> axi_hbm_port(3).ar.bits.addr
		instHbm.io.AXI_03_ARBURST  	<> axi_hbm_port(3).ar.bits.burst
		instHbm.io.AXI_03_ARID     	<> axi_hbm_port(3).ar.bits.id
		instHbm.io.AXI_03_ARLEN    	<> axi_hbm_port(3).ar.bits.len
		instHbm.io.AXI_03_ARSIZE   	<> axi_hbm_port(3).ar.bits.size
		instHbm.io.AXI_03_ARVALID  	<> axi_hbm_port(3).ar.valid
		instHbm.io.AXI_03_ARREADY  	<> axi_hbm_port(3).ar.ready
		instHbm.io.AXI_03_AWADDR   	<> axi_hbm_port(3).aw.bits.addr
		instHbm.io.AXI_03_AWBURST  	<> axi_hbm_port(3).aw.bits.burst
		instHbm.io.AXI_03_AWID     	<> axi_hbm_port(3).aw.bits.id
		instHbm.io.AXI_03_AWLEN    	<> axi_hbm_port(3).aw.bits.len
		instHbm.io.AXI_03_AWSIZE   	<> axi_hbm_port(3).aw.bits.size
		instHbm.io.AXI_03_AWVALID  	<> axi_hbm_port(3).aw.valid
		instHbm.io.AXI_03_AWREADY  	<> axi_hbm_port(3).aw.ready
		instHbm.io.AXI_03_WDATA    	<> axi_hbm_port(3).w.bits.data
		instHbm.io.AXI_03_WLAST    	<> axi_hbm_port(3).w.bits.last
		instHbm.io.AXI_03_WSTRB    	<> axi_hbm_port(3).w.bits.strb
		instHbm.io.AXI_03_WVALID   	<> axi_hbm_port(3).w.valid
		instHbm.io.AXI_03_WREADY   	<> axi_hbm_port(3).w.ready
		instHbm.io.AXI_03_RDATA    	<> axi_hbm_port(3).r.bits.data
		instHbm.io.AXI_03_RID      	<> axi_hbm_port(3).r.bits.id
		instHbm.io.AXI_03_RLAST    	<> axi_hbm_port(3).r.bits.last
		instHbm.io.AXI_03_RRESP    	<> axi_hbm_port(3).r.bits.resp
		instHbm.io.AXI_03_RVALID   	<> axi_hbm_port(3).r.valid
		instHbm.io.AXI_03_RREADY   	<> axi_hbm_port(3).r.ready
		instHbm.io.AXI_03_BID      	<> axi_hbm_port(3).b.bits.id
		instHbm.io.AXI_03_BRESP    	<> axi_hbm_port(3).b.bits.resp
		instHbm.io.AXI_03_BVALID   	<> axi_hbm_port(3).b.valid
		instHbm.io.AXI_03_BREADY   	<> axi_hbm_port(3).b.ready
		instHbm.io.AXI_03_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_03_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_04_ACLK		<> axiAclk
		instHbm.io.AXI_04_ARESET_N	<> axiLocked
		instHbm.io.AXI_04_ARADDR   	<> axi_hbm_port(4).ar.bits.addr
		instHbm.io.AXI_04_ARBURST  	<> axi_hbm_port(4).ar.bits.burst
		instHbm.io.AXI_04_ARID     	<> axi_hbm_port(4).ar.bits.id
		instHbm.io.AXI_04_ARLEN    	<> axi_hbm_port(4).ar.bits.len
		instHbm.io.AXI_04_ARSIZE   	<> axi_hbm_port(4).ar.bits.size
		instHbm.io.AXI_04_ARVALID  	<> axi_hbm_port(4).ar.valid
		instHbm.io.AXI_04_ARREADY  	<> axi_hbm_port(4).ar.ready
		instHbm.io.AXI_04_AWADDR   	<> axi_hbm_port(4).aw.bits.addr
		instHbm.io.AXI_04_AWBURST  	<> axi_hbm_port(4).aw.bits.burst
		instHbm.io.AXI_04_AWID     	<> axi_hbm_port(4).aw.bits.id
		instHbm.io.AXI_04_AWLEN    	<> axi_hbm_port(4).aw.bits.len
		instHbm.io.AXI_04_AWSIZE   	<> axi_hbm_port(4).aw.bits.size
		instHbm.io.AXI_04_AWVALID  	<> axi_hbm_port(4).aw.valid
		instHbm.io.AXI_04_AWREADY  	<> axi_hbm_port(4).aw.ready
		instHbm.io.AXI_04_WDATA    	<> axi_hbm_port(4).w.bits.data
		instHbm.io.AXI_04_WLAST    	<> axi_hbm_port(4).w.bits.last
		instHbm.io.AXI_04_WSTRB    	<> axi_hbm_port(4).w.bits.strb
		instHbm.io.AXI_04_WVALID   	<> axi_hbm_port(4).w.valid
		instHbm.io.AXI_04_WREADY   	<> axi_hbm_port(4).w.ready
		instHbm.io.AXI_04_RDATA    	<> axi_hbm_port(4).r.bits.data
		instHbm.io.AXI_04_RID      	<> axi_hbm_port(4).r.bits.id
		instHbm.io.AXI_04_RLAST    	<> axi_hbm_port(4).r.bits.last
		instHbm.io.AXI_04_RRESP    	<> axi_hbm_port(4).r.bits.resp
		instHbm.io.AXI_04_RVALID   	<> axi_hbm_port(4).r.valid
		instHbm.io.AXI_04_RREADY   	<> axi_hbm_port(4).r.ready
		instHbm.io.AXI_04_BID      	<> axi_hbm_port(4).b.bits.id
		instHbm.io.AXI_04_BRESP    	<> axi_hbm_port(4).b.bits.resp
		instHbm.io.AXI_04_BVALID   	<> axi_hbm_port(4).b.valid
		instHbm.io.AXI_04_BREADY   	<> axi_hbm_port(4).b.ready
		instHbm.io.AXI_04_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_04_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_05_ACLK		<> axiAclk
		instHbm.io.AXI_05_ARESET_N	<> axiLocked
		instHbm.io.AXI_05_ARADDR   	<> axi_hbm_port(5).ar.bits.addr
		instHbm.io.AXI_05_ARBURST  	<> axi_hbm_port(5).ar.bits.burst
		instHbm.io.AXI_05_ARID     	<> axi_hbm_port(5).ar.bits.id
		instHbm.io.AXI_05_ARLEN    	<> axi_hbm_port(5).ar.bits.len
		instHbm.io.AXI_05_ARSIZE   	<> axi_hbm_port(5).ar.bits.size
		instHbm.io.AXI_05_ARVALID  	<> axi_hbm_port(5).ar.valid
		instHbm.io.AXI_05_ARREADY  	<> axi_hbm_port(5).ar.ready
		instHbm.io.AXI_05_AWADDR   	<> axi_hbm_port(5).aw.bits.addr
		instHbm.io.AXI_05_AWBURST  	<> axi_hbm_port(5).aw.bits.burst
		instHbm.io.AXI_05_AWID     	<> axi_hbm_port(5).aw.bits.id
		instHbm.io.AXI_05_AWLEN    	<> axi_hbm_port(5).aw.bits.len
		instHbm.io.AXI_05_AWSIZE   	<> axi_hbm_port(5).aw.bits.size
		instHbm.io.AXI_05_AWVALID  	<> axi_hbm_port(5).aw.valid
		instHbm.io.AXI_05_AWREADY  	<> axi_hbm_port(5).aw.ready
		instHbm.io.AXI_05_WDATA    	<> axi_hbm_port(5).w.bits.data
		instHbm.io.AXI_05_WLAST    	<> axi_hbm_port(5).w.bits.last
		instHbm.io.AXI_05_WSTRB    	<> axi_hbm_port(5).w.bits.strb
		instHbm.io.AXI_05_WVALID   	<> axi_hbm_port(5).w.valid
		instHbm.io.AXI_05_WREADY   	<> axi_hbm_port(5).w.ready
		instHbm.io.AXI_05_RDATA    	<> axi_hbm_port(5).r.bits.data
		instHbm.io.AXI_05_RID      	<> axi_hbm_port(5).r.bits.id
		instHbm.io.AXI_05_RLAST    	<> axi_hbm_port(5).r.bits.last
		instHbm.io.AXI_05_RRESP    	<> axi_hbm_port(5).r.bits.resp
		instHbm.io.AXI_05_RVALID   	<> axi_hbm_port(5).r.valid
		instHbm.io.AXI_05_RREADY   	<> axi_hbm_port(5).r.ready
		instHbm.io.AXI_05_BID      	<> axi_hbm_port(5).b.bits.id
		instHbm.io.AXI_05_BRESP    	<> axi_hbm_port(5).b.bits.resp
		instHbm.io.AXI_05_BVALID   	<> axi_hbm_port(5).b.valid
		instHbm.io.AXI_05_BREADY   	<> axi_hbm_port(5).b.ready
		instHbm.io.AXI_05_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_05_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_06_ACLK		<> axiAclk
		instHbm.io.AXI_06_ARESET_N	<> axiLocked
		instHbm.io.AXI_06_ARADDR   	<> axi_hbm_port(6).ar.bits.addr
		instHbm.io.AXI_06_ARBURST  	<> axi_hbm_port(6).ar.bits.burst
		instHbm.io.AXI_06_ARID     	<> axi_hbm_port(6).ar.bits.id
		instHbm.io.AXI_06_ARLEN    	<> axi_hbm_port(6).ar.bits.len
		instHbm.io.AXI_06_ARSIZE   	<> axi_hbm_port(6).ar.bits.size
		instHbm.io.AXI_06_ARVALID  	<> axi_hbm_port(6).ar.valid
		instHbm.io.AXI_06_ARREADY  	<> axi_hbm_port(6).ar.ready
		instHbm.io.AXI_06_AWADDR   	<> axi_hbm_port(6).aw.bits.addr
		instHbm.io.AXI_06_AWBURST  	<> axi_hbm_port(6).aw.bits.burst
		instHbm.io.AXI_06_AWID     	<> axi_hbm_port(6).aw.bits.id
		instHbm.io.AXI_06_AWLEN    	<> axi_hbm_port(6).aw.bits.len
		instHbm.io.AXI_06_AWSIZE   	<> axi_hbm_port(6).aw.bits.size
		instHbm.io.AXI_06_AWVALID  	<> axi_hbm_port(6).aw.valid
		instHbm.io.AXI_06_AWREADY  	<> axi_hbm_port(6).aw.ready
		instHbm.io.AXI_06_WDATA    	<> axi_hbm_port(6).w.bits.data
		instHbm.io.AXI_06_WLAST    	<> axi_hbm_port(6).w.bits.last
		instHbm.io.AXI_06_WSTRB    	<> axi_hbm_port(6).w.bits.strb
		instHbm.io.AXI_06_WVALID   	<> axi_hbm_port(6).w.valid
		instHbm.io.AXI_06_WREADY   	<> axi_hbm_port(6).w.ready
		instHbm.io.AXI_06_RDATA    	<> axi_hbm_port(6).r.bits.data
		instHbm.io.AXI_06_RID      	<> axi_hbm_port(6).r.bits.id
		instHbm.io.AXI_06_RLAST    	<> axi_hbm_port(6).r.bits.last
		instHbm.io.AXI_06_RRESP    	<> axi_hbm_port(6).r.bits.resp
		instHbm.io.AXI_06_RVALID   	<> axi_hbm_port(6).r.valid
		instHbm.io.AXI_06_RREADY   	<> axi_hbm_port(6).r.ready
		instHbm.io.AXI_06_BID      	<> axi_hbm_port(6).b.bits.id
		instHbm.io.AXI_06_BRESP    	<> axi_hbm_port(6).b.bits.resp
		instHbm.io.AXI_06_BVALID   	<> axi_hbm_port(6).b.valid
		instHbm.io.AXI_06_BREADY   	<> axi_hbm_port(6).b.ready
		instHbm.io.AXI_06_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_06_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_07_ACLK		<> axiAclk
		instHbm.io.AXI_07_ARESET_N	<> axiLocked
		instHbm.io.AXI_07_ARADDR   	<> axi_hbm_port(7).ar.bits.addr
		instHbm.io.AXI_07_ARBURST  	<> axi_hbm_port(7).ar.bits.burst
		instHbm.io.AXI_07_ARID     	<> axi_hbm_port(7).ar.bits.id
		instHbm.io.AXI_07_ARLEN    	<> axi_hbm_port(7).ar.bits.len
		instHbm.io.AXI_07_ARSIZE   	<> axi_hbm_port(7).ar.bits.size
		instHbm.io.AXI_07_ARVALID  	<> axi_hbm_port(7).ar.valid
		instHbm.io.AXI_07_ARREADY  	<> axi_hbm_port(7).ar.ready
		instHbm.io.AXI_07_AWADDR   	<> axi_hbm_port(7).aw.bits.addr
		instHbm.io.AXI_07_AWBURST  	<> axi_hbm_port(7).aw.bits.burst
		instHbm.io.AXI_07_AWID     	<> axi_hbm_port(7).aw.bits.id
		instHbm.io.AXI_07_AWLEN    	<> axi_hbm_port(7).aw.bits.len
		instHbm.io.AXI_07_AWSIZE   	<> axi_hbm_port(7).aw.bits.size
		instHbm.io.AXI_07_AWVALID  	<> axi_hbm_port(7).aw.valid
		instHbm.io.AXI_07_AWREADY  	<> axi_hbm_port(7).aw.ready
		instHbm.io.AXI_07_WDATA    	<> axi_hbm_port(7).w.bits.data
		instHbm.io.AXI_07_WLAST    	<> axi_hbm_port(7).w.bits.last
		instHbm.io.AXI_07_WSTRB    	<> axi_hbm_port(7).w.bits.strb
		instHbm.io.AXI_07_WVALID   	<> axi_hbm_port(7).w.valid
		instHbm.io.AXI_07_WREADY   	<> axi_hbm_port(7).w.ready
		instHbm.io.AXI_07_RDATA    	<> axi_hbm_port(7).r.bits.data
		instHbm.io.AXI_07_RID      	<> axi_hbm_port(7).r.bits.id
		instHbm.io.AXI_07_RLAST    	<> axi_hbm_port(7).r.bits.last
		instHbm.io.AXI_07_RRESP    	<> axi_hbm_port(7).r.bits.resp
		instHbm.io.AXI_07_RVALID   	<> axi_hbm_port(7).r.valid
		instHbm.io.AXI_07_RREADY   	<> axi_hbm_port(7).r.ready
		instHbm.io.AXI_07_BID      	<> axi_hbm_port(7).b.bits.id
		instHbm.io.AXI_07_BRESP    	<> axi_hbm_port(7).b.bits.resp
		instHbm.io.AXI_07_BVALID   	<> axi_hbm_port(7).b.valid
		instHbm.io.AXI_07_BREADY   	<> axi_hbm_port(7).b.ready
		instHbm.io.AXI_07_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_07_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_08_ACLK		<> axiAclk
		instHbm.io.AXI_08_ARESET_N	<> axiLocked
		instHbm.io.AXI_08_ARADDR   	<> axi_hbm_port(8).ar.bits.addr
		instHbm.io.AXI_08_ARBURST  	<> axi_hbm_port(8).ar.bits.burst
		instHbm.io.AXI_08_ARID     	<> axi_hbm_port(8).ar.bits.id
		instHbm.io.AXI_08_ARLEN    	<> axi_hbm_port(8).ar.bits.len
		instHbm.io.AXI_08_ARSIZE   	<> axi_hbm_port(8).ar.bits.size
		instHbm.io.AXI_08_ARVALID  	<> axi_hbm_port(8).ar.valid
		instHbm.io.AXI_08_ARREADY  	<> axi_hbm_port(8).ar.ready
		instHbm.io.AXI_08_AWADDR   	<> axi_hbm_port(8).aw.bits.addr
		instHbm.io.AXI_08_AWBURST  	<> axi_hbm_port(8).aw.bits.burst
		instHbm.io.AXI_08_AWID     	<> axi_hbm_port(8).aw.bits.id
		instHbm.io.AXI_08_AWLEN    	<> axi_hbm_port(8).aw.bits.len
		instHbm.io.AXI_08_AWSIZE   	<> axi_hbm_port(8).aw.bits.size
		instHbm.io.AXI_08_AWVALID  	<> axi_hbm_port(8).aw.valid
		instHbm.io.AXI_08_AWREADY  	<> axi_hbm_port(8).aw.ready
		instHbm.io.AXI_08_WDATA    	<> axi_hbm_port(8).w.bits.data
		instHbm.io.AXI_08_WLAST    	<> axi_hbm_port(8).w.bits.last
		instHbm.io.AXI_08_WSTRB    	<> axi_hbm_port(8).w.bits.strb
		instHbm.io.AXI_08_WVALID   	<> axi_hbm_port(8).w.valid
		instHbm.io.AXI_08_WREADY   	<> axi_hbm_port(8).w.ready
		instHbm.io.AXI_08_RDATA    	<> axi_hbm_port(8).r.bits.data
		instHbm.io.AXI_08_RID      	<> axi_hbm_port(8).r.bits.id
		instHbm.io.AXI_08_RLAST    	<> axi_hbm_port(8).r.bits.last
		instHbm.io.AXI_08_RRESP    	<> axi_hbm_port(8).r.bits.resp
		instHbm.io.AXI_08_RVALID   	<> axi_hbm_port(8).r.valid
		instHbm.io.AXI_08_RREADY   	<> axi_hbm_port(8).r.ready
		instHbm.io.AXI_08_BID      	<> axi_hbm_port(8).b.bits.id
		instHbm.io.AXI_08_BRESP    	<> axi_hbm_port(8).b.bits.resp
		instHbm.io.AXI_08_BVALID   	<> axi_hbm_port(8).b.valid
		instHbm.io.AXI_08_BREADY   	<> axi_hbm_port(8).b.ready
		instHbm.io.AXI_08_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_08_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_09_ACLK		<> axiAclk
		instHbm.io.AXI_09_ARESET_N	<> axiLocked
		instHbm.io.AXI_09_ARADDR   	<> axi_hbm_port(9).ar.bits.addr
		instHbm.io.AXI_09_ARBURST  	<> axi_hbm_port(9).ar.bits.burst
		instHbm.io.AXI_09_ARID     	<> axi_hbm_port(9).ar.bits.id
		instHbm.io.AXI_09_ARLEN    	<> axi_hbm_port(9).ar.bits.len
		instHbm.io.AXI_09_ARSIZE   	<> axi_hbm_port(9).ar.bits.size
		instHbm.io.AXI_09_ARVALID  	<> axi_hbm_port(9).ar.valid
		instHbm.io.AXI_09_ARREADY  	<> axi_hbm_port(9).ar.ready
		instHbm.io.AXI_09_AWADDR   	<> axi_hbm_port(9).aw.bits.addr
		instHbm.io.AXI_09_AWBURST  	<> axi_hbm_port(9).aw.bits.burst
		instHbm.io.AXI_09_AWID     	<> axi_hbm_port(9).aw.bits.id
		instHbm.io.AXI_09_AWLEN    	<> axi_hbm_port(9).aw.bits.len
		instHbm.io.AXI_09_AWSIZE   	<> axi_hbm_port(9).aw.bits.size
		instHbm.io.AXI_09_AWVALID  	<> axi_hbm_port(9).aw.valid
		instHbm.io.AXI_09_AWREADY  	<> axi_hbm_port(9).aw.ready
		instHbm.io.AXI_09_WDATA    	<> axi_hbm_port(9).w.bits.data
		instHbm.io.AXI_09_WLAST    	<> axi_hbm_port(9).w.bits.last
		instHbm.io.AXI_09_WSTRB    	<> axi_hbm_port(9).w.bits.strb
		instHbm.io.AXI_09_WVALID   	<> axi_hbm_port(9).w.valid
		instHbm.io.AXI_09_WREADY   	<> axi_hbm_port(9).w.ready
		instHbm.io.AXI_09_RDATA    	<> axi_hbm_port(9).r.bits.data
		instHbm.io.AXI_09_RID      	<> axi_hbm_port(9).r.bits.id
		instHbm.io.AXI_09_RLAST    	<> axi_hbm_port(9).r.bits.last
		instHbm.io.AXI_09_RRESP    	<> axi_hbm_port(9).r.bits.resp
		instHbm.io.AXI_09_RVALID   	<> axi_hbm_port(9).r.valid
		instHbm.io.AXI_09_RREADY   	<> axi_hbm_port(9).r.ready
		instHbm.io.AXI_09_BID      	<> axi_hbm_port(9).b.bits.id
		instHbm.io.AXI_09_BRESP    	<> axi_hbm_port(9).b.bits.resp
		instHbm.io.AXI_09_BVALID   	<> axi_hbm_port(9).b.valid
		instHbm.io.AXI_09_BREADY   	<> axi_hbm_port(9).b.ready
		instHbm.io.AXI_09_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_09_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_10_ACLK		<> axiAclk
		instHbm.io.AXI_10_ARESET_N	<> axiLocked
		instHbm.io.AXI_10_ARADDR   	<> axi_hbm_port(10).ar.bits.addr
		instHbm.io.AXI_10_ARBURST  	<> axi_hbm_port(10).ar.bits.burst
		instHbm.io.AXI_10_ARID     	<> axi_hbm_port(10).ar.bits.id
		instHbm.io.AXI_10_ARLEN    	<> axi_hbm_port(10).ar.bits.len
		instHbm.io.AXI_10_ARSIZE   	<> axi_hbm_port(10).ar.bits.size
		instHbm.io.AXI_10_ARVALID  	<> axi_hbm_port(10).ar.valid
		instHbm.io.AXI_10_ARREADY  	<> axi_hbm_port(10).ar.ready
		instHbm.io.AXI_10_AWADDR   	<> axi_hbm_port(10).aw.bits.addr
		instHbm.io.AXI_10_AWBURST  	<> axi_hbm_port(10).aw.bits.burst
		instHbm.io.AXI_10_AWID     	<> axi_hbm_port(10).aw.bits.id
		instHbm.io.AXI_10_AWLEN    	<> axi_hbm_port(10).aw.bits.len
		instHbm.io.AXI_10_AWSIZE   	<> axi_hbm_port(10).aw.bits.size
		instHbm.io.AXI_10_AWVALID  	<> axi_hbm_port(10).aw.valid
		instHbm.io.AXI_10_AWREADY  	<> axi_hbm_port(10).aw.ready
		instHbm.io.AXI_10_WDATA    	<> axi_hbm_port(10).w.bits.data
		instHbm.io.AXI_10_WLAST    	<> axi_hbm_port(10).w.bits.last
		instHbm.io.AXI_10_WSTRB    	<> axi_hbm_port(10).w.bits.strb
		instHbm.io.AXI_10_WVALID   	<> axi_hbm_port(10).w.valid
		instHbm.io.AXI_10_WREADY   	<> axi_hbm_port(10).w.ready
		instHbm.io.AXI_10_RDATA    	<> axi_hbm_port(10).r.bits.data
		instHbm.io.AXI_10_RID      	<> axi_hbm_port(10).r.bits.id
		instHbm.io.AXI_10_RLAST    	<> axi_hbm_port(10).r.bits.last
		instHbm.io.AXI_10_RRESP    	<> axi_hbm_port(10).r.bits.resp
		instHbm.io.AXI_10_RVALID   	<> axi_hbm_port(10).r.valid
		instHbm.io.AXI_10_RREADY   	<> axi_hbm_port(10).r.ready
		instHbm.io.AXI_10_BID      	<> axi_hbm_port(10).b.bits.id
		instHbm.io.AXI_10_BRESP    	<> axi_hbm_port(10).b.bits.resp
		instHbm.io.AXI_10_BVALID   	<> axi_hbm_port(10).b.valid
		instHbm.io.AXI_10_BREADY   	<> axi_hbm_port(10).b.ready
		instHbm.io.AXI_10_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_10_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_11_ACLK		<> axiAclk
		instHbm.io.AXI_11_ARESET_N	<> axiLocked
		instHbm.io.AXI_11_ARADDR   	<> axi_hbm_port(11).ar.bits.addr
		instHbm.io.AXI_11_ARBURST  	<> axi_hbm_port(11).ar.bits.burst
		instHbm.io.AXI_11_ARID     	<> axi_hbm_port(11).ar.bits.id
		instHbm.io.AXI_11_ARLEN    	<> axi_hbm_port(11).ar.bits.len
		instHbm.io.AXI_11_ARSIZE   	<> axi_hbm_port(11).ar.bits.size
		instHbm.io.AXI_11_ARVALID  	<> axi_hbm_port(11).ar.valid
		instHbm.io.AXI_11_ARREADY  	<> axi_hbm_port(11).ar.ready
		instHbm.io.AXI_11_AWADDR   	<> axi_hbm_port(11).aw.bits.addr
		instHbm.io.AXI_11_AWBURST  	<> axi_hbm_port(11).aw.bits.burst
		instHbm.io.AXI_11_AWID     	<> axi_hbm_port(11).aw.bits.id
		instHbm.io.AXI_11_AWLEN    	<> axi_hbm_port(11).aw.bits.len
		instHbm.io.AXI_11_AWSIZE   	<> axi_hbm_port(11).aw.bits.size
		instHbm.io.AXI_11_AWVALID  	<> axi_hbm_port(11).aw.valid
		instHbm.io.AXI_11_AWREADY  	<> axi_hbm_port(11).aw.ready
		instHbm.io.AXI_11_WDATA    	<> axi_hbm_port(11).w.bits.data
		instHbm.io.AXI_11_WLAST    	<> axi_hbm_port(11).w.bits.last
		instHbm.io.AXI_11_WSTRB    	<> axi_hbm_port(11).w.bits.strb
		instHbm.io.AXI_11_WVALID   	<> axi_hbm_port(11).w.valid
		instHbm.io.AXI_11_WREADY   	<> axi_hbm_port(11).w.ready
		instHbm.io.AXI_11_RDATA    	<> axi_hbm_port(11).r.bits.data
		instHbm.io.AXI_11_RID      	<> axi_hbm_port(11).r.bits.id
		instHbm.io.AXI_11_RLAST    	<> axi_hbm_port(11).r.bits.last
		instHbm.io.AXI_11_RRESP    	<> axi_hbm_port(11).r.bits.resp
		instHbm.io.AXI_11_RVALID   	<> axi_hbm_port(11).r.valid
		instHbm.io.AXI_11_RREADY   	<> axi_hbm_port(11).r.ready
		instHbm.io.AXI_11_BID      	<> axi_hbm_port(11).b.bits.id
		instHbm.io.AXI_11_BRESP    	<> axi_hbm_port(11).b.bits.resp
		instHbm.io.AXI_11_BVALID   	<> axi_hbm_port(11).b.valid
		instHbm.io.AXI_11_BREADY   	<> axi_hbm_port(11).b.ready
		instHbm.io.AXI_11_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_11_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_12_ACLK		<> axiAclk
		instHbm.io.AXI_12_ARESET_N	<> axiLocked
		instHbm.io.AXI_12_ARADDR   	<> axi_hbm_port(12).ar.bits.addr
		instHbm.io.AXI_12_ARBURST  	<> axi_hbm_port(12).ar.bits.burst
		instHbm.io.AXI_12_ARID     	<> axi_hbm_port(12).ar.bits.id
		instHbm.io.AXI_12_ARLEN    	<> axi_hbm_port(12).ar.bits.len
		instHbm.io.AXI_12_ARSIZE   	<> axi_hbm_port(12).ar.bits.size
		instHbm.io.AXI_12_ARVALID  	<> axi_hbm_port(12).ar.valid
		instHbm.io.AXI_12_ARREADY  	<> axi_hbm_port(12).ar.ready
		instHbm.io.AXI_12_AWADDR   	<> axi_hbm_port(12).aw.bits.addr
		instHbm.io.AXI_12_AWBURST  	<> axi_hbm_port(12).aw.bits.burst
		instHbm.io.AXI_12_AWID     	<> axi_hbm_port(12).aw.bits.id
		instHbm.io.AXI_12_AWLEN    	<> axi_hbm_port(12).aw.bits.len
		instHbm.io.AXI_12_AWSIZE   	<> axi_hbm_port(12).aw.bits.size
		instHbm.io.AXI_12_AWVALID  	<> axi_hbm_port(12).aw.valid
		instHbm.io.AXI_12_AWREADY  	<> axi_hbm_port(12).aw.ready
		instHbm.io.AXI_12_WDATA    	<> axi_hbm_port(12).w.bits.data
		instHbm.io.AXI_12_WLAST    	<> axi_hbm_port(12).w.bits.last
		instHbm.io.AXI_12_WSTRB    	<> axi_hbm_port(12).w.bits.strb
		instHbm.io.AXI_12_WVALID   	<> axi_hbm_port(12).w.valid
		instHbm.io.AXI_12_WREADY   	<> axi_hbm_port(12).w.ready
		instHbm.io.AXI_12_RDATA    	<> axi_hbm_port(12).r.bits.data
		instHbm.io.AXI_12_RID      	<> axi_hbm_port(12).r.bits.id
		instHbm.io.AXI_12_RLAST    	<> axi_hbm_port(12).r.bits.last
		instHbm.io.AXI_12_RRESP    	<> axi_hbm_port(12).r.bits.resp
		instHbm.io.AXI_12_RVALID   	<> axi_hbm_port(12).r.valid
		instHbm.io.AXI_12_RREADY   	<> axi_hbm_port(12).r.ready
		instHbm.io.AXI_12_BID      	<> axi_hbm_port(12).b.bits.id
		instHbm.io.AXI_12_BRESP    	<> axi_hbm_port(12).b.bits.resp
		instHbm.io.AXI_12_BVALID   	<> axi_hbm_port(12).b.valid
		instHbm.io.AXI_12_BREADY   	<> axi_hbm_port(12).b.ready
		instHbm.io.AXI_12_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_12_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_13_ACLK		<> axiAclk
		instHbm.io.AXI_13_ARESET_N	<> axiLocked
		instHbm.io.AXI_13_ARADDR   	<> axi_hbm_port(13).ar.bits.addr
		instHbm.io.AXI_13_ARBURST  	<> axi_hbm_port(13).ar.bits.burst
		instHbm.io.AXI_13_ARID     	<> axi_hbm_port(13).ar.bits.id
		instHbm.io.AXI_13_ARLEN    	<> axi_hbm_port(13).ar.bits.len
		instHbm.io.AXI_13_ARSIZE   	<> axi_hbm_port(13).ar.bits.size
		instHbm.io.AXI_13_ARVALID  	<> axi_hbm_port(13).ar.valid
		instHbm.io.AXI_13_ARREADY  	<> axi_hbm_port(13).ar.ready
		instHbm.io.AXI_13_AWADDR   	<> axi_hbm_port(13).aw.bits.addr
		instHbm.io.AXI_13_AWBURST  	<> axi_hbm_port(13).aw.bits.burst
		instHbm.io.AXI_13_AWID     	<> axi_hbm_port(13).aw.bits.id
		instHbm.io.AXI_13_AWLEN    	<> axi_hbm_port(13).aw.bits.len
		instHbm.io.AXI_13_AWSIZE   	<> axi_hbm_port(13).aw.bits.size
		instHbm.io.AXI_13_AWVALID  	<> axi_hbm_port(13).aw.valid
		instHbm.io.AXI_13_AWREADY  	<> axi_hbm_port(13).aw.ready
		instHbm.io.AXI_13_WDATA    	<> axi_hbm_port(13).w.bits.data
		instHbm.io.AXI_13_WLAST    	<> axi_hbm_port(13).w.bits.last
		instHbm.io.AXI_13_WSTRB    	<> axi_hbm_port(13).w.bits.strb
		instHbm.io.AXI_13_WVALID   	<> axi_hbm_port(13).w.valid
		instHbm.io.AXI_13_WREADY   	<> axi_hbm_port(13).w.ready
		instHbm.io.AXI_13_RDATA    	<> axi_hbm_port(13).r.bits.data
		instHbm.io.AXI_13_RID      	<> axi_hbm_port(13).r.bits.id
		instHbm.io.AXI_13_RLAST    	<> axi_hbm_port(13).r.bits.last
		instHbm.io.AXI_13_RRESP    	<> axi_hbm_port(13).r.bits.resp
		instHbm.io.AXI_13_RVALID   	<> axi_hbm_port(13).r.valid
		instHbm.io.AXI_13_RREADY   	<> axi_hbm_port(13).r.ready
		instHbm.io.AXI_13_BID      	<> axi_hbm_port(13).b.bits.id
		instHbm.io.AXI_13_BRESP    	<> axi_hbm_port(13).b.bits.resp
		instHbm.io.AXI_13_BVALID   	<> axi_hbm_port(13).b.valid
		instHbm.io.AXI_13_BREADY   	<> axi_hbm_port(13).b.ready
		instHbm.io.AXI_13_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_13_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_14_ACLK		<> axiAclk
		instHbm.io.AXI_14_ARESET_N	<> axiLocked
		instHbm.io.AXI_14_ARADDR   	<> axi_hbm_port(14).ar.bits.addr
		instHbm.io.AXI_14_ARBURST  	<> axi_hbm_port(14).ar.bits.burst
		instHbm.io.AXI_14_ARID     	<> axi_hbm_port(14).ar.bits.id
		instHbm.io.AXI_14_ARLEN    	<> axi_hbm_port(14).ar.bits.len
		instHbm.io.AXI_14_ARSIZE   	<> axi_hbm_port(14).ar.bits.size
		instHbm.io.AXI_14_ARVALID  	<> axi_hbm_port(14).ar.valid
		instHbm.io.AXI_14_ARREADY  	<> axi_hbm_port(14).ar.ready
		instHbm.io.AXI_14_AWADDR   	<> axi_hbm_port(14).aw.bits.addr
		instHbm.io.AXI_14_AWBURST  	<> axi_hbm_port(14).aw.bits.burst
		instHbm.io.AXI_14_AWID     	<> axi_hbm_port(14).aw.bits.id
		instHbm.io.AXI_14_AWLEN    	<> axi_hbm_port(14).aw.bits.len
		instHbm.io.AXI_14_AWSIZE   	<> axi_hbm_port(14).aw.bits.size
		instHbm.io.AXI_14_AWVALID  	<> axi_hbm_port(14).aw.valid
		instHbm.io.AXI_14_AWREADY  	<> axi_hbm_port(14).aw.ready
		instHbm.io.AXI_14_WDATA    	<> axi_hbm_port(14).w.bits.data
		instHbm.io.AXI_14_WLAST    	<> axi_hbm_port(14).w.bits.last
		instHbm.io.AXI_14_WSTRB    	<> axi_hbm_port(14).w.bits.strb
		instHbm.io.AXI_14_WVALID   	<> axi_hbm_port(14).w.valid
		instHbm.io.AXI_14_WREADY   	<> axi_hbm_port(14).w.ready
		instHbm.io.AXI_14_RDATA    	<> axi_hbm_port(14).r.bits.data
		instHbm.io.AXI_14_RID      	<> axi_hbm_port(14).r.bits.id
		instHbm.io.AXI_14_RLAST    	<> axi_hbm_port(14).r.bits.last
		instHbm.io.AXI_14_RRESP    	<> axi_hbm_port(14).r.bits.resp
		instHbm.io.AXI_14_RVALID   	<> axi_hbm_port(14).r.valid
		instHbm.io.AXI_14_RREADY   	<> axi_hbm_port(14).r.ready
		instHbm.io.AXI_14_BID      	<> axi_hbm_port(14).b.bits.id
		instHbm.io.AXI_14_BRESP    	<> axi_hbm_port(14).b.bits.resp
		instHbm.io.AXI_14_BVALID   	<> axi_hbm_port(14).b.valid
		instHbm.io.AXI_14_BREADY   	<> axi_hbm_port(14).b.ready
		instHbm.io.AXI_14_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_14_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_15_ACLK		<> axiAclk
		instHbm.io.AXI_15_ARESET_N	<> axiLocked
		instHbm.io.AXI_15_ARADDR   	<> axi_hbm_port(15).ar.bits.addr
		instHbm.io.AXI_15_ARBURST  	<> axi_hbm_port(15).ar.bits.burst
		instHbm.io.AXI_15_ARID     	<> axi_hbm_port(15).ar.bits.id
		instHbm.io.AXI_15_ARLEN    	<> axi_hbm_port(15).ar.bits.len
		instHbm.io.AXI_15_ARSIZE   	<> axi_hbm_port(15).ar.bits.size
		instHbm.io.AXI_15_ARVALID  	<> axi_hbm_port(15).ar.valid
		instHbm.io.AXI_15_ARREADY  	<> axi_hbm_port(15).ar.ready
		instHbm.io.AXI_15_AWADDR   	<> axi_hbm_port(15).aw.bits.addr
		instHbm.io.AXI_15_AWBURST  	<> axi_hbm_port(15).aw.bits.burst
		instHbm.io.AXI_15_AWID     	<> axi_hbm_port(15).aw.bits.id
		instHbm.io.AXI_15_AWLEN    	<> axi_hbm_port(15).aw.bits.len
		instHbm.io.AXI_15_AWSIZE   	<> axi_hbm_port(15).aw.bits.size
		instHbm.io.AXI_15_AWVALID  	<> axi_hbm_port(15).aw.valid
		instHbm.io.AXI_15_AWREADY  	<> axi_hbm_port(15).aw.ready
		instHbm.io.AXI_15_WDATA    	<> axi_hbm_port(15).w.bits.data
		instHbm.io.AXI_15_WLAST    	<> axi_hbm_port(15).w.bits.last
		instHbm.io.AXI_15_WSTRB    	<> axi_hbm_port(15).w.bits.strb
		instHbm.io.AXI_15_WVALID   	<> axi_hbm_port(15).w.valid
		instHbm.io.AXI_15_WREADY   	<> axi_hbm_port(15).w.ready
		instHbm.io.AXI_15_RDATA    	<> axi_hbm_port(15).r.bits.data
		instHbm.io.AXI_15_RID      	<> axi_hbm_port(15).r.bits.id
		instHbm.io.AXI_15_RLAST    	<> axi_hbm_port(15).r.bits.last
		instHbm.io.AXI_15_RRESP    	<> axi_hbm_port(15).r.bits.resp
		instHbm.io.AXI_15_RVALID   	<> axi_hbm_port(15).r.valid
		instHbm.io.AXI_15_RREADY   	<> axi_hbm_port(15).r.ready
		instHbm.io.AXI_15_BID      	<> axi_hbm_port(15).b.bits.id
		instHbm.io.AXI_15_BRESP    	<> axi_hbm_port(15).b.bits.resp
		instHbm.io.AXI_15_BVALID   	<> axi_hbm_port(15).b.valid
		instHbm.io.AXI_15_BREADY   	<> axi_hbm_port(15).b.ready
		instHbm.io.AXI_15_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_15_RDATA_PARITY	<> DontCare
	}
	hbmInit1(instHbm, axi_hbm_port, axiAclk, axiLocked)
	
	val hbmInit2 = (
		instHbm : HBMBlackBox,
		axi_hbm_port: Vec[AXI],
		axiAclk : Clock,
		axiLocked : UInt
	) => {
		instHbm.io.AXI_16_ACLK		<> axiAclk
		instHbm.io.AXI_16_ARESET_N	<> axiLocked
		instHbm.io.AXI_16_ARADDR   	<> axi_hbm_port(16).ar.bits.addr
		instHbm.io.AXI_16_ARBURST  	<> axi_hbm_port(16).ar.bits.burst
		instHbm.io.AXI_16_ARID     	<> axi_hbm_port(16).ar.bits.id
		instHbm.io.AXI_16_ARLEN    	<> axi_hbm_port(16).ar.bits.len
		instHbm.io.AXI_16_ARSIZE   	<> axi_hbm_port(16).ar.bits.size
		instHbm.io.AXI_16_ARVALID  	<> axi_hbm_port(16).ar.valid
		instHbm.io.AXI_16_ARREADY  	<> axi_hbm_port(16).ar.ready
		instHbm.io.AXI_16_AWADDR   	<> axi_hbm_port(16).aw.bits.addr
		instHbm.io.AXI_16_AWBURST  	<> axi_hbm_port(16).aw.bits.burst
		instHbm.io.AXI_16_AWID     	<> axi_hbm_port(16).aw.bits.id
		instHbm.io.AXI_16_AWLEN    	<> axi_hbm_port(16).aw.bits.len
		instHbm.io.AXI_16_AWSIZE   	<> axi_hbm_port(16).aw.bits.size
		instHbm.io.AXI_16_AWVALID  	<> axi_hbm_port(16).aw.valid
		instHbm.io.AXI_16_AWREADY  	<> axi_hbm_port(16).aw.ready
		instHbm.io.AXI_16_WDATA    	<> axi_hbm_port(16).w.bits.data
		instHbm.io.AXI_16_WLAST    	<> axi_hbm_port(16).w.bits.last
		instHbm.io.AXI_16_WSTRB    	<> axi_hbm_port(16).w.bits.strb
		instHbm.io.AXI_16_WVALID   	<> axi_hbm_port(16).w.valid
		instHbm.io.AXI_16_WREADY   	<> axi_hbm_port(16).w.ready
		instHbm.io.AXI_16_RDATA    	<> axi_hbm_port(16).r.bits.data
		instHbm.io.AXI_16_RID      	<> axi_hbm_port(16).r.bits.id
		instHbm.io.AXI_16_RLAST    	<> axi_hbm_port(16).r.bits.last
		instHbm.io.AXI_16_RRESP    	<> axi_hbm_port(16).r.bits.resp
		instHbm.io.AXI_16_RVALID   	<> axi_hbm_port(16).r.valid
		instHbm.io.AXI_16_RREADY   	<> axi_hbm_port(16).r.ready
		instHbm.io.AXI_16_BID      	<> axi_hbm_port(16).b.bits.id
		instHbm.io.AXI_16_BRESP    	<> axi_hbm_port(16).b.bits.resp
		instHbm.io.AXI_16_BVALID   	<> axi_hbm_port(16).b.valid
		instHbm.io.AXI_16_BREADY   	<> axi_hbm_port(16).b.ready
		instHbm.io.AXI_16_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_16_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_17_ACLK		<> axiAclk
		instHbm.io.AXI_17_ARESET_N	<> axiLocked
		instHbm.io.AXI_17_ARADDR   	<> axi_hbm_port(17).ar.bits.addr
		instHbm.io.AXI_17_ARBURST  	<> axi_hbm_port(17).ar.bits.burst
		instHbm.io.AXI_17_ARID     	<> axi_hbm_port(17).ar.bits.id
		instHbm.io.AXI_17_ARLEN    	<> axi_hbm_port(17).ar.bits.len
		instHbm.io.AXI_17_ARSIZE   	<> axi_hbm_port(17).ar.bits.size
		instHbm.io.AXI_17_ARVALID  	<> axi_hbm_port(17).ar.valid
		instHbm.io.AXI_17_ARREADY  	<> axi_hbm_port(17).ar.ready
		instHbm.io.AXI_17_AWADDR   	<> axi_hbm_port(17).aw.bits.addr
		instHbm.io.AXI_17_AWBURST  	<> axi_hbm_port(17).aw.bits.burst
		instHbm.io.AXI_17_AWID     	<> axi_hbm_port(17).aw.bits.id
		instHbm.io.AXI_17_AWLEN    	<> axi_hbm_port(17).aw.bits.len
		instHbm.io.AXI_17_AWSIZE   	<> axi_hbm_port(17).aw.bits.size
		instHbm.io.AXI_17_AWVALID  	<> axi_hbm_port(17).aw.valid
		instHbm.io.AXI_17_AWREADY  	<> axi_hbm_port(17).aw.ready
		instHbm.io.AXI_17_WDATA    	<> axi_hbm_port(17).w.bits.data
		instHbm.io.AXI_17_WLAST    	<> axi_hbm_port(17).w.bits.last
		instHbm.io.AXI_17_WSTRB    	<> axi_hbm_port(17).w.bits.strb
		instHbm.io.AXI_17_WVALID   	<> axi_hbm_port(17).w.valid
		instHbm.io.AXI_17_WREADY   	<> axi_hbm_port(17).w.ready
		instHbm.io.AXI_17_RDATA    	<> axi_hbm_port(17).r.bits.data
		instHbm.io.AXI_17_RID      	<> axi_hbm_port(17).r.bits.id
		instHbm.io.AXI_17_RLAST    	<> axi_hbm_port(17).r.bits.last
		instHbm.io.AXI_17_RRESP    	<> axi_hbm_port(17).r.bits.resp
		instHbm.io.AXI_17_RVALID   	<> axi_hbm_port(17).r.valid
		instHbm.io.AXI_17_RREADY   	<> axi_hbm_port(17).r.ready
		instHbm.io.AXI_17_BID      	<> axi_hbm_port(17).b.bits.id
		instHbm.io.AXI_17_BRESP    	<> axi_hbm_port(17).b.bits.resp
		instHbm.io.AXI_17_BVALID   	<> axi_hbm_port(17).b.valid
		instHbm.io.AXI_17_BREADY   	<> axi_hbm_port(17).b.ready
		instHbm.io.AXI_17_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_17_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_18_ACLK		<> axiAclk
		instHbm.io.AXI_18_ARESET_N	<> axiLocked
		instHbm.io.AXI_18_ARADDR   	<> axi_hbm_port(18).ar.bits.addr
		instHbm.io.AXI_18_ARBURST  	<> axi_hbm_port(18).ar.bits.burst
		instHbm.io.AXI_18_ARID     	<> axi_hbm_port(18).ar.bits.id
		instHbm.io.AXI_18_ARLEN    	<> axi_hbm_port(18).ar.bits.len
		instHbm.io.AXI_18_ARSIZE   	<> axi_hbm_port(18).ar.bits.size
		instHbm.io.AXI_18_ARVALID  	<> axi_hbm_port(18).ar.valid
		instHbm.io.AXI_18_ARREADY  	<> axi_hbm_port(18).ar.ready
		instHbm.io.AXI_18_AWADDR   	<> axi_hbm_port(18).aw.bits.addr
		instHbm.io.AXI_18_AWBURST  	<> axi_hbm_port(18).aw.bits.burst
		instHbm.io.AXI_18_AWID     	<> axi_hbm_port(18).aw.bits.id
		instHbm.io.AXI_18_AWLEN    	<> axi_hbm_port(18).aw.bits.len
		instHbm.io.AXI_18_AWSIZE   	<> axi_hbm_port(18).aw.bits.size
		instHbm.io.AXI_18_AWVALID  	<> axi_hbm_port(18).aw.valid
		instHbm.io.AXI_18_AWREADY  	<> axi_hbm_port(18).aw.ready
		instHbm.io.AXI_18_WDATA    	<> axi_hbm_port(18).w.bits.data
		instHbm.io.AXI_18_WLAST    	<> axi_hbm_port(18).w.bits.last
		instHbm.io.AXI_18_WSTRB    	<> axi_hbm_port(18).w.bits.strb
		instHbm.io.AXI_18_WVALID   	<> axi_hbm_port(18).w.valid
		instHbm.io.AXI_18_WREADY   	<> axi_hbm_port(18).w.ready
		instHbm.io.AXI_18_RDATA    	<> axi_hbm_port(18).r.bits.data
		instHbm.io.AXI_18_RID      	<> axi_hbm_port(18).r.bits.id
		instHbm.io.AXI_18_RLAST    	<> axi_hbm_port(18).r.bits.last
		instHbm.io.AXI_18_RRESP    	<> axi_hbm_port(18).r.bits.resp
		instHbm.io.AXI_18_RVALID   	<> axi_hbm_port(18).r.valid
		instHbm.io.AXI_18_RREADY   	<> axi_hbm_port(18).r.ready
		instHbm.io.AXI_18_BID      	<> axi_hbm_port(18).b.bits.id
		instHbm.io.AXI_18_BRESP    	<> axi_hbm_port(18).b.bits.resp
		instHbm.io.AXI_18_BVALID   	<> axi_hbm_port(18).b.valid
		instHbm.io.AXI_18_BREADY   	<> axi_hbm_port(18).b.ready
		instHbm.io.AXI_18_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_18_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_19_ACLK		<> axiAclk
		instHbm.io.AXI_19_ARESET_N	<> axiLocked
		instHbm.io.AXI_19_ARADDR   	<> axi_hbm_port(19).ar.bits.addr
		instHbm.io.AXI_19_ARBURST  	<> axi_hbm_port(19).ar.bits.burst
		instHbm.io.AXI_19_ARID     	<> axi_hbm_port(19).ar.bits.id
		instHbm.io.AXI_19_ARLEN    	<> axi_hbm_port(19).ar.bits.len
		instHbm.io.AXI_19_ARSIZE   	<> axi_hbm_port(19).ar.bits.size
		instHbm.io.AXI_19_ARVALID  	<> axi_hbm_port(19).ar.valid
		instHbm.io.AXI_19_ARREADY  	<> axi_hbm_port(19).ar.ready
		instHbm.io.AXI_19_AWADDR   	<> axi_hbm_port(19).aw.bits.addr
		instHbm.io.AXI_19_AWBURST  	<> axi_hbm_port(19).aw.bits.burst
		instHbm.io.AXI_19_AWID     	<> axi_hbm_port(19).aw.bits.id
		instHbm.io.AXI_19_AWLEN    	<> axi_hbm_port(19).aw.bits.len
		instHbm.io.AXI_19_AWSIZE   	<> axi_hbm_port(19).aw.bits.size
		instHbm.io.AXI_19_AWVALID  	<> axi_hbm_port(19).aw.valid
		instHbm.io.AXI_19_AWREADY  	<> axi_hbm_port(19).aw.ready
		instHbm.io.AXI_19_WDATA    	<> axi_hbm_port(19).w.bits.data
		instHbm.io.AXI_19_WLAST    	<> axi_hbm_port(19).w.bits.last
		instHbm.io.AXI_19_WSTRB    	<> axi_hbm_port(19).w.bits.strb
		instHbm.io.AXI_19_WVALID   	<> axi_hbm_port(19).w.valid
		instHbm.io.AXI_19_WREADY   	<> axi_hbm_port(19).w.ready
		instHbm.io.AXI_19_RDATA    	<> axi_hbm_port(19).r.bits.data
		instHbm.io.AXI_19_RID      	<> axi_hbm_port(19).r.bits.id
		instHbm.io.AXI_19_RLAST    	<> axi_hbm_port(19).r.bits.last
		instHbm.io.AXI_19_RRESP    	<> axi_hbm_port(19).r.bits.resp
		instHbm.io.AXI_19_RVALID   	<> axi_hbm_port(19).r.valid
		instHbm.io.AXI_19_RREADY   	<> axi_hbm_port(19).r.ready
		instHbm.io.AXI_19_BID      	<> axi_hbm_port(19).b.bits.id
		instHbm.io.AXI_19_BRESP    	<> axi_hbm_port(19).b.bits.resp
		instHbm.io.AXI_19_BVALID   	<> axi_hbm_port(19).b.valid
		instHbm.io.AXI_19_BREADY   	<> axi_hbm_port(19).b.ready
		instHbm.io.AXI_19_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_19_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_20_ACLK		<> axiAclk
		instHbm.io.AXI_20_ARESET_N	<> axiLocked
		instHbm.io.AXI_20_ARADDR   	<> axi_hbm_port(20).ar.bits.addr
		instHbm.io.AXI_20_ARBURST  	<> axi_hbm_port(20).ar.bits.burst
		instHbm.io.AXI_20_ARID     	<> axi_hbm_port(20).ar.bits.id
		instHbm.io.AXI_20_ARLEN    	<> axi_hbm_port(20).ar.bits.len
		instHbm.io.AXI_20_ARSIZE   	<> axi_hbm_port(20).ar.bits.size
		instHbm.io.AXI_20_ARVALID  	<> axi_hbm_port(20).ar.valid
		instHbm.io.AXI_20_ARREADY  	<> axi_hbm_port(20).ar.ready
		instHbm.io.AXI_20_AWADDR   	<> axi_hbm_port(20).aw.bits.addr
		instHbm.io.AXI_20_AWBURST  	<> axi_hbm_port(20).aw.bits.burst
		instHbm.io.AXI_20_AWID     	<> axi_hbm_port(20).aw.bits.id
		instHbm.io.AXI_20_AWLEN    	<> axi_hbm_port(20).aw.bits.len
		instHbm.io.AXI_20_AWSIZE   	<> axi_hbm_port(20).aw.bits.size
		instHbm.io.AXI_20_AWVALID  	<> axi_hbm_port(20).aw.valid
		instHbm.io.AXI_20_AWREADY  	<> axi_hbm_port(20).aw.ready
		instHbm.io.AXI_20_WDATA    	<> axi_hbm_port(20).w.bits.data
		instHbm.io.AXI_20_WLAST    	<> axi_hbm_port(20).w.bits.last
		instHbm.io.AXI_20_WSTRB    	<> axi_hbm_port(20).w.bits.strb
		instHbm.io.AXI_20_WVALID   	<> axi_hbm_port(20).w.valid
		instHbm.io.AXI_20_WREADY   	<> axi_hbm_port(20).w.ready
		instHbm.io.AXI_20_RDATA    	<> axi_hbm_port(20).r.bits.data
		instHbm.io.AXI_20_RID      	<> axi_hbm_port(20).r.bits.id
		instHbm.io.AXI_20_RLAST    	<> axi_hbm_port(20).r.bits.last
		instHbm.io.AXI_20_RRESP    	<> axi_hbm_port(20).r.bits.resp
		instHbm.io.AXI_20_RVALID   	<> axi_hbm_port(20).r.valid
		instHbm.io.AXI_20_RREADY   	<> axi_hbm_port(20).r.ready
		instHbm.io.AXI_20_BID      	<> axi_hbm_port(20).b.bits.id
		instHbm.io.AXI_20_BRESP    	<> axi_hbm_port(20).b.bits.resp
		instHbm.io.AXI_20_BVALID   	<> axi_hbm_port(20).b.valid
		instHbm.io.AXI_20_BREADY   	<> axi_hbm_port(20).b.ready
		instHbm.io.AXI_20_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_20_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_21_ACLK		<> axiAclk
		instHbm.io.AXI_21_ARESET_N	<> axiLocked
		instHbm.io.AXI_21_ARADDR   	<> axi_hbm_port(21).ar.bits.addr
		instHbm.io.AXI_21_ARBURST  	<> axi_hbm_port(21).ar.bits.burst
		instHbm.io.AXI_21_ARID     	<> axi_hbm_port(21).ar.bits.id
		instHbm.io.AXI_21_ARLEN    	<> axi_hbm_port(21).ar.bits.len
		instHbm.io.AXI_21_ARSIZE   	<> axi_hbm_port(21).ar.bits.size
		instHbm.io.AXI_21_ARVALID  	<> axi_hbm_port(21).ar.valid
		instHbm.io.AXI_21_ARREADY  	<> axi_hbm_port(21).ar.ready
		instHbm.io.AXI_21_AWADDR   	<> axi_hbm_port(21).aw.bits.addr
		instHbm.io.AXI_21_AWBURST  	<> axi_hbm_port(21).aw.bits.burst
		instHbm.io.AXI_21_AWID     	<> axi_hbm_port(21).aw.bits.id
		instHbm.io.AXI_21_AWLEN    	<> axi_hbm_port(21).aw.bits.len
		instHbm.io.AXI_21_AWSIZE   	<> axi_hbm_port(21).aw.bits.size
		instHbm.io.AXI_21_AWVALID  	<> axi_hbm_port(21).aw.valid
		instHbm.io.AXI_21_AWREADY  	<> axi_hbm_port(21).aw.ready
		instHbm.io.AXI_21_WDATA    	<> axi_hbm_port(21).w.bits.data
		instHbm.io.AXI_21_WLAST    	<> axi_hbm_port(21).w.bits.last
		instHbm.io.AXI_21_WSTRB    	<> axi_hbm_port(21).w.bits.strb
		instHbm.io.AXI_21_WVALID   	<> axi_hbm_port(21).w.valid
		instHbm.io.AXI_21_WREADY   	<> axi_hbm_port(21).w.ready
		instHbm.io.AXI_21_RDATA    	<> axi_hbm_port(21).r.bits.data
		instHbm.io.AXI_21_RID      	<> axi_hbm_port(21).r.bits.id
		instHbm.io.AXI_21_RLAST    	<> axi_hbm_port(21).r.bits.last
		instHbm.io.AXI_21_RRESP    	<> axi_hbm_port(21).r.bits.resp
		instHbm.io.AXI_21_RVALID   	<> axi_hbm_port(21).r.valid
		instHbm.io.AXI_21_RREADY   	<> axi_hbm_port(21).r.ready
		instHbm.io.AXI_21_BID      	<> axi_hbm_port(21).b.bits.id
		instHbm.io.AXI_21_BRESP    	<> axi_hbm_port(21).b.bits.resp
		instHbm.io.AXI_21_BVALID   	<> axi_hbm_port(21).b.valid
		instHbm.io.AXI_21_BREADY   	<> axi_hbm_port(21).b.ready
		instHbm.io.AXI_21_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_21_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_22_ACLK		<> axiAclk
		instHbm.io.AXI_22_ARESET_N	<> axiLocked
		instHbm.io.AXI_22_ARADDR   	<> axi_hbm_port(22).ar.bits.addr
		instHbm.io.AXI_22_ARBURST  	<> axi_hbm_port(22).ar.bits.burst
		instHbm.io.AXI_22_ARID     	<> axi_hbm_port(22).ar.bits.id
		instHbm.io.AXI_22_ARLEN    	<> axi_hbm_port(22).ar.bits.len
		instHbm.io.AXI_22_ARSIZE   	<> axi_hbm_port(22).ar.bits.size
		instHbm.io.AXI_22_ARVALID  	<> axi_hbm_port(22).ar.valid
		instHbm.io.AXI_22_ARREADY  	<> axi_hbm_port(22).ar.ready
		instHbm.io.AXI_22_AWADDR   	<> axi_hbm_port(22).aw.bits.addr
		instHbm.io.AXI_22_AWBURST  	<> axi_hbm_port(22).aw.bits.burst
		instHbm.io.AXI_22_AWID     	<> axi_hbm_port(22).aw.bits.id
		instHbm.io.AXI_22_AWLEN    	<> axi_hbm_port(22).aw.bits.len
		instHbm.io.AXI_22_AWSIZE   	<> axi_hbm_port(22).aw.bits.size
		instHbm.io.AXI_22_AWVALID  	<> axi_hbm_port(22).aw.valid
		instHbm.io.AXI_22_AWREADY  	<> axi_hbm_port(22).aw.ready
		instHbm.io.AXI_22_WDATA    	<> axi_hbm_port(22).w.bits.data
		instHbm.io.AXI_22_WLAST    	<> axi_hbm_port(22).w.bits.last
		instHbm.io.AXI_22_WSTRB    	<> axi_hbm_port(22).w.bits.strb
		instHbm.io.AXI_22_WVALID   	<> axi_hbm_port(22).w.valid
		instHbm.io.AXI_22_WREADY   	<> axi_hbm_port(22).w.ready
		instHbm.io.AXI_22_RDATA    	<> axi_hbm_port(22).r.bits.data
		instHbm.io.AXI_22_RID      	<> axi_hbm_port(22).r.bits.id
		instHbm.io.AXI_22_RLAST    	<> axi_hbm_port(22).r.bits.last
		instHbm.io.AXI_22_RRESP    	<> axi_hbm_port(22).r.bits.resp
		instHbm.io.AXI_22_RVALID   	<> axi_hbm_port(22).r.valid
		instHbm.io.AXI_22_RREADY   	<> axi_hbm_port(22).r.ready
		instHbm.io.AXI_22_BID      	<> axi_hbm_port(22).b.bits.id
		instHbm.io.AXI_22_BRESP    	<> axi_hbm_port(22).b.bits.resp
		instHbm.io.AXI_22_BVALID   	<> axi_hbm_port(22).b.valid
		instHbm.io.AXI_22_BREADY   	<> axi_hbm_port(22).b.ready
		instHbm.io.AXI_22_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_22_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_23_ACLK		<> axiAclk
		instHbm.io.AXI_23_ARESET_N	<> axiLocked
		instHbm.io.AXI_23_ARADDR   	<> axi_hbm_port(23).ar.bits.addr
		instHbm.io.AXI_23_ARBURST  	<> axi_hbm_port(23).ar.bits.burst
		instHbm.io.AXI_23_ARID     	<> axi_hbm_port(23).ar.bits.id
		instHbm.io.AXI_23_ARLEN    	<> axi_hbm_port(23).ar.bits.len
		instHbm.io.AXI_23_ARSIZE   	<> axi_hbm_port(23).ar.bits.size
		instHbm.io.AXI_23_ARVALID  	<> axi_hbm_port(23).ar.valid
		instHbm.io.AXI_23_ARREADY  	<> axi_hbm_port(23).ar.ready
		instHbm.io.AXI_23_AWADDR   	<> axi_hbm_port(23).aw.bits.addr
		instHbm.io.AXI_23_AWBURST  	<> axi_hbm_port(23).aw.bits.burst
		instHbm.io.AXI_23_AWID     	<> axi_hbm_port(23).aw.bits.id
		instHbm.io.AXI_23_AWLEN    	<> axi_hbm_port(23).aw.bits.len
		instHbm.io.AXI_23_AWSIZE   	<> axi_hbm_port(23).aw.bits.size
		instHbm.io.AXI_23_AWVALID  	<> axi_hbm_port(23).aw.valid
		instHbm.io.AXI_23_AWREADY  	<> axi_hbm_port(23).aw.ready
		instHbm.io.AXI_23_WDATA    	<> axi_hbm_port(23).w.bits.data
		instHbm.io.AXI_23_WLAST    	<> axi_hbm_port(23).w.bits.last
		instHbm.io.AXI_23_WSTRB    	<> axi_hbm_port(23).w.bits.strb
		instHbm.io.AXI_23_WVALID   	<> axi_hbm_port(23).w.valid
		instHbm.io.AXI_23_WREADY   	<> axi_hbm_port(23).w.ready
		instHbm.io.AXI_23_RDATA    	<> axi_hbm_port(23).r.bits.data
		instHbm.io.AXI_23_RID      	<> axi_hbm_port(23).r.bits.id
		instHbm.io.AXI_23_RLAST    	<> axi_hbm_port(23).r.bits.last
		instHbm.io.AXI_23_RRESP    	<> axi_hbm_port(23).r.bits.resp
		instHbm.io.AXI_23_RVALID   	<> axi_hbm_port(23).r.valid
		instHbm.io.AXI_23_RREADY   	<> axi_hbm_port(23).r.ready
		instHbm.io.AXI_23_BID      	<> axi_hbm_port(23).b.bits.id
		instHbm.io.AXI_23_BRESP    	<> axi_hbm_port(23).b.bits.resp
		instHbm.io.AXI_23_BVALID   	<> axi_hbm_port(23).b.valid
		instHbm.io.AXI_23_BREADY   	<> axi_hbm_port(23).b.ready
		instHbm.io.AXI_23_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_23_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_24_ACLK		<> axiAclk
		instHbm.io.AXI_24_ARESET_N	<> axiLocked
		instHbm.io.AXI_24_ARADDR   	<> axi_hbm_port(24).ar.bits.addr
		instHbm.io.AXI_24_ARBURST  	<> axi_hbm_port(24).ar.bits.burst
		instHbm.io.AXI_24_ARID     	<> axi_hbm_port(24).ar.bits.id
		instHbm.io.AXI_24_ARLEN    	<> axi_hbm_port(24).ar.bits.len
		instHbm.io.AXI_24_ARSIZE   	<> axi_hbm_port(24).ar.bits.size
		instHbm.io.AXI_24_ARVALID  	<> axi_hbm_port(24).ar.valid
		instHbm.io.AXI_24_ARREADY  	<> axi_hbm_port(24).ar.ready
		instHbm.io.AXI_24_AWADDR   	<> axi_hbm_port(24).aw.bits.addr
		instHbm.io.AXI_24_AWBURST  	<> axi_hbm_port(24).aw.bits.burst
		instHbm.io.AXI_24_AWID     	<> axi_hbm_port(24).aw.bits.id
		instHbm.io.AXI_24_AWLEN    	<> axi_hbm_port(24).aw.bits.len
		instHbm.io.AXI_24_AWSIZE   	<> axi_hbm_port(24).aw.bits.size
		instHbm.io.AXI_24_AWVALID  	<> axi_hbm_port(24).aw.valid
		instHbm.io.AXI_24_AWREADY  	<> axi_hbm_port(24).aw.ready
		instHbm.io.AXI_24_WDATA    	<> axi_hbm_port(24).w.bits.data
		instHbm.io.AXI_24_WLAST    	<> axi_hbm_port(24).w.bits.last
		instHbm.io.AXI_24_WSTRB    	<> axi_hbm_port(24).w.bits.strb
		instHbm.io.AXI_24_WVALID   	<> axi_hbm_port(24).w.valid
		instHbm.io.AXI_24_WREADY   	<> axi_hbm_port(24).w.ready
		instHbm.io.AXI_24_RDATA    	<> axi_hbm_port(24).r.bits.data
		instHbm.io.AXI_24_RID      	<> axi_hbm_port(24).r.bits.id
		instHbm.io.AXI_24_RLAST    	<> axi_hbm_port(24).r.bits.last
		instHbm.io.AXI_24_RRESP    	<> axi_hbm_port(24).r.bits.resp
		instHbm.io.AXI_24_RVALID   	<> axi_hbm_port(24).r.valid
		instHbm.io.AXI_24_RREADY   	<> axi_hbm_port(24).r.ready
		instHbm.io.AXI_24_BID      	<> axi_hbm_port(24).b.bits.id
		instHbm.io.AXI_24_BRESP    	<> axi_hbm_port(24).b.bits.resp
		instHbm.io.AXI_24_BVALID   	<> axi_hbm_port(24).b.valid
		instHbm.io.AXI_24_BREADY   	<> axi_hbm_port(24).b.ready
		instHbm.io.AXI_24_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_24_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_25_ACLK		<> axiAclk
		instHbm.io.AXI_25_ARESET_N	<> axiLocked
		instHbm.io.AXI_25_ARADDR   	<> axi_hbm_port(25).ar.bits.addr
		instHbm.io.AXI_25_ARBURST  	<> axi_hbm_port(25).ar.bits.burst
		instHbm.io.AXI_25_ARID     	<> axi_hbm_port(25).ar.bits.id
		instHbm.io.AXI_25_ARLEN    	<> axi_hbm_port(25).ar.bits.len
		instHbm.io.AXI_25_ARSIZE   	<> axi_hbm_port(25).ar.bits.size
		instHbm.io.AXI_25_ARVALID  	<> axi_hbm_port(25).ar.valid
		instHbm.io.AXI_25_ARREADY  	<> axi_hbm_port(25).ar.ready
		instHbm.io.AXI_25_AWADDR   	<> axi_hbm_port(25).aw.bits.addr
		instHbm.io.AXI_25_AWBURST  	<> axi_hbm_port(25).aw.bits.burst
		instHbm.io.AXI_25_AWID     	<> axi_hbm_port(25).aw.bits.id
		instHbm.io.AXI_25_AWLEN    	<> axi_hbm_port(25).aw.bits.len
		instHbm.io.AXI_25_AWSIZE   	<> axi_hbm_port(25).aw.bits.size
		instHbm.io.AXI_25_AWVALID  	<> axi_hbm_port(25).aw.valid
		instHbm.io.AXI_25_AWREADY  	<> axi_hbm_port(25).aw.ready
		instHbm.io.AXI_25_WDATA    	<> axi_hbm_port(25).w.bits.data
		instHbm.io.AXI_25_WLAST    	<> axi_hbm_port(25).w.bits.last
		instHbm.io.AXI_25_WSTRB    	<> axi_hbm_port(25).w.bits.strb
		instHbm.io.AXI_25_WVALID   	<> axi_hbm_port(25).w.valid
		instHbm.io.AXI_25_WREADY   	<> axi_hbm_port(25).w.ready
		instHbm.io.AXI_25_RDATA    	<> axi_hbm_port(25).r.bits.data
		instHbm.io.AXI_25_RID      	<> axi_hbm_port(25).r.bits.id
		instHbm.io.AXI_25_RLAST    	<> axi_hbm_port(25).r.bits.last
		instHbm.io.AXI_25_RRESP    	<> axi_hbm_port(25).r.bits.resp
		instHbm.io.AXI_25_RVALID   	<> axi_hbm_port(25).r.valid
		instHbm.io.AXI_25_RREADY   	<> axi_hbm_port(25).r.ready
		instHbm.io.AXI_25_BID      	<> axi_hbm_port(25).b.bits.id
		instHbm.io.AXI_25_BRESP    	<> axi_hbm_port(25).b.bits.resp
		instHbm.io.AXI_25_BVALID   	<> axi_hbm_port(25).b.valid
		instHbm.io.AXI_25_BREADY   	<> axi_hbm_port(25).b.ready
		instHbm.io.AXI_25_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_25_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_26_ACLK		<> axiAclk
		instHbm.io.AXI_26_ARESET_N	<> axiLocked
		instHbm.io.AXI_26_ARADDR   	<> axi_hbm_port(26).ar.bits.addr
		instHbm.io.AXI_26_ARBURST  	<> axi_hbm_port(26).ar.bits.burst
		instHbm.io.AXI_26_ARID     	<> axi_hbm_port(26).ar.bits.id
		instHbm.io.AXI_26_ARLEN    	<> axi_hbm_port(26).ar.bits.len
		instHbm.io.AXI_26_ARSIZE   	<> axi_hbm_port(26).ar.bits.size
		instHbm.io.AXI_26_ARVALID  	<> axi_hbm_port(26).ar.valid
		instHbm.io.AXI_26_ARREADY  	<> axi_hbm_port(26).ar.ready
		instHbm.io.AXI_26_AWADDR   	<> axi_hbm_port(26).aw.bits.addr
		instHbm.io.AXI_26_AWBURST  	<> axi_hbm_port(26).aw.bits.burst
		instHbm.io.AXI_26_AWID     	<> axi_hbm_port(26).aw.bits.id
		instHbm.io.AXI_26_AWLEN    	<> axi_hbm_port(26).aw.bits.len
		instHbm.io.AXI_26_AWSIZE   	<> axi_hbm_port(26).aw.bits.size
		instHbm.io.AXI_26_AWVALID  	<> axi_hbm_port(26).aw.valid
		instHbm.io.AXI_26_AWREADY  	<> axi_hbm_port(26).aw.ready
		instHbm.io.AXI_26_WDATA    	<> axi_hbm_port(26).w.bits.data
		instHbm.io.AXI_26_WLAST    	<> axi_hbm_port(26).w.bits.last
		instHbm.io.AXI_26_WSTRB    	<> axi_hbm_port(26).w.bits.strb
		instHbm.io.AXI_26_WVALID   	<> axi_hbm_port(26).w.valid
		instHbm.io.AXI_26_WREADY   	<> axi_hbm_port(26).w.ready
		instHbm.io.AXI_26_RDATA    	<> axi_hbm_port(26).r.bits.data
		instHbm.io.AXI_26_RID      	<> axi_hbm_port(26).r.bits.id
		instHbm.io.AXI_26_RLAST    	<> axi_hbm_port(26).r.bits.last
		instHbm.io.AXI_26_RRESP    	<> axi_hbm_port(26).r.bits.resp
		instHbm.io.AXI_26_RVALID   	<> axi_hbm_port(26).r.valid
		instHbm.io.AXI_26_RREADY   	<> axi_hbm_port(26).r.ready
		instHbm.io.AXI_26_BID      	<> axi_hbm_port(26).b.bits.id
		instHbm.io.AXI_26_BRESP    	<> axi_hbm_port(26).b.bits.resp
		instHbm.io.AXI_26_BVALID   	<> axi_hbm_port(26).b.valid
		instHbm.io.AXI_26_BREADY   	<> axi_hbm_port(26).b.ready
		instHbm.io.AXI_26_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_26_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_27_ACLK		<> axiAclk
		instHbm.io.AXI_27_ARESET_N	<> axiLocked
		instHbm.io.AXI_27_ARADDR   	<> axi_hbm_port(27).ar.bits.addr
		instHbm.io.AXI_27_ARBURST  	<> axi_hbm_port(27).ar.bits.burst
		instHbm.io.AXI_27_ARID     	<> axi_hbm_port(27).ar.bits.id
		instHbm.io.AXI_27_ARLEN    	<> axi_hbm_port(27).ar.bits.len
		instHbm.io.AXI_27_ARSIZE   	<> axi_hbm_port(27).ar.bits.size
		instHbm.io.AXI_27_ARVALID  	<> axi_hbm_port(27).ar.valid
		instHbm.io.AXI_27_ARREADY  	<> axi_hbm_port(27).ar.ready
		instHbm.io.AXI_27_AWADDR   	<> axi_hbm_port(27).aw.bits.addr
		instHbm.io.AXI_27_AWBURST  	<> axi_hbm_port(27).aw.bits.burst
		instHbm.io.AXI_27_AWID     	<> axi_hbm_port(27).aw.bits.id
		instHbm.io.AXI_27_AWLEN    	<> axi_hbm_port(27).aw.bits.len
		instHbm.io.AXI_27_AWSIZE   	<> axi_hbm_port(27).aw.bits.size
		instHbm.io.AXI_27_AWVALID  	<> axi_hbm_port(27).aw.valid
		instHbm.io.AXI_27_AWREADY  	<> axi_hbm_port(27).aw.ready
		instHbm.io.AXI_27_WDATA    	<> axi_hbm_port(27).w.bits.data
		instHbm.io.AXI_27_WLAST    	<> axi_hbm_port(27).w.bits.last
		instHbm.io.AXI_27_WSTRB    	<> axi_hbm_port(27).w.bits.strb
		instHbm.io.AXI_27_WVALID   	<> axi_hbm_port(27).w.valid
		instHbm.io.AXI_27_WREADY   	<> axi_hbm_port(27).w.ready
		instHbm.io.AXI_27_RDATA    	<> axi_hbm_port(27).r.bits.data
		instHbm.io.AXI_27_RID      	<> axi_hbm_port(27).r.bits.id
		instHbm.io.AXI_27_RLAST    	<> axi_hbm_port(27).r.bits.last
		instHbm.io.AXI_27_RRESP    	<> axi_hbm_port(27).r.bits.resp
		instHbm.io.AXI_27_RVALID   	<> axi_hbm_port(27).r.valid
		instHbm.io.AXI_27_RREADY   	<> axi_hbm_port(27).r.ready
		instHbm.io.AXI_27_BID      	<> axi_hbm_port(27).b.bits.id
		instHbm.io.AXI_27_BRESP    	<> axi_hbm_port(27).b.bits.resp
		instHbm.io.AXI_27_BVALID   	<> axi_hbm_port(27).b.valid
		instHbm.io.AXI_27_BREADY   	<> axi_hbm_port(27).b.ready
		instHbm.io.AXI_27_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_27_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_28_ACLK		<> axiAclk
		instHbm.io.AXI_28_ARESET_N	<> axiLocked
		instHbm.io.AXI_28_ARADDR   	<> axi_hbm_port(28).ar.bits.addr
		instHbm.io.AXI_28_ARBURST  	<> axi_hbm_port(28).ar.bits.burst
		instHbm.io.AXI_28_ARID     	<> axi_hbm_port(28).ar.bits.id
		instHbm.io.AXI_28_ARLEN    	<> axi_hbm_port(28).ar.bits.len
		instHbm.io.AXI_28_ARSIZE   	<> axi_hbm_port(28).ar.bits.size
		instHbm.io.AXI_28_ARVALID  	<> axi_hbm_port(28).ar.valid
		instHbm.io.AXI_28_ARREADY  	<> axi_hbm_port(28).ar.ready
		instHbm.io.AXI_28_AWADDR   	<> axi_hbm_port(28).aw.bits.addr
		instHbm.io.AXI_28_AWBURST  	<> axi_hbm_port(28).aw.bits.burst
		instHbm.io.AXI_28_AWID     	<> axi_hbm_port(28).aw.bits.id
		instHbm.io.AXI_28_AWLEN    	<> axi_hbm_port(28).aw.bits.len
		instHbm.io.AXI_28_AWSIZE   	<> axi_hbm_port(28).aw.bits.size
		instHbm.io.AXI_28_AWVALID  	<> axi_hbm_port(28).aw.valid
		instHbm.io.AXI_28_AWREADY  	<> axi_hbm_port(28).aw.ready
		instHbm.io.AXI_28_WDATA    	<> axi_hbm_port(28).w.bits.data
		instHbm.io.AXI_28_WLAST    	<> axi_hbm_port(28).w.bits.last
		instHbm.io.AXI_28_WSTRB    	<> axi_hbm_port(28).w.bits.strb
		instHbm.io.AXI_28_WVALID   	<> axi_hbm_port(28).w.valid
		instHbm.io.AXI_28_WREADY   	<> axi_hbm_port(28).w.ready
		instHbm.io.AXI_28_RDATA    	<> axi_hbm_port(28).r.bits.data
		instHbm.io.AXI_28_RID      	<> axi_hbm_port(28).r.bits.id
		instHbm.io.AXI_28_RLAST    	<> axi_hbm_port(28).r.bits.last
		instHbm.io.AXI_28_RRESP    	<> axi_hbm_port(28).r.bits.resp
		instHbm.io.AXI_28_RVALID   	<> axi_hbm_port(28).r.valid
		instHbm.io.AXI_28_RREADY   	<> axi_hbm_port(28).r.ready
		instHbm.io.AXI_28_BID      	<> axi_hbm_port(28).b.bits.id
		instHbm.io.AXI_28_BRESP    	<> axi_hbm_port(28).b.bits.resp
		instHbm.io.AXI_28_BVALID   	<> axi_hbm_port(28).b.valid
		instHbm.io.AXI_28_BREADY   	<> axi_hbm_port(28).b.ready
		instHbm.io.AXI_28_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_28_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_29_ACLK		<> axiAclk
		instHbm.io.AXI_29_ARESET_N	<> axiLocked
		instHbm.io.AXI_29_ARADDR   	<> axi_hbm_port(29).ar.bits.addr
		instHbm.io.AXI_29_ARBURST  	<> axi_hbm_port(29).ar.bits.burst
		instHbm.io.AXI_29_ARID     	<> axi_hbm_port(29).ar.bits.id
		instHbm.io.AXI_29_ARLEN    	<> axi_hbm_port(29).ar.bits.len
		instHbm.io.AXI_29_ARSIZE   	<> axi_hbm_port(29).ar.bits.size
		instHbm.io.AXI_29_ARVALID  	<> axi_hbm_port(29).ar.valid
		instHbm.io.AXI_29_ARREADY  	<> axi_hbm_port(29).ar.ready
		instHbm.io.AXI_29_AWADDR   	<> axi_hbm_port(29).aw.bits.addr
		instHbm.io.AXI_29_AWBURST  	<> axi_hbm_port(29).aw.bits.burst
		instHbm.io.AXI_29_AWID     	<> axi_hbm_port(29).aw.bits.id
		instHbm.io.AXI_29_AWLEN    	<> axi_hbm_port(29).aw.bits.len
		instHbm.io.AXI_29_AWSIZE   	<> axi_hbm_port(29).aw.bits.size
		instHbm.io.AXI_29_AWVALID  	<> axi_hbm_port(29).aw.valid
		instHbm.io.AXI_29_AWREADY  	<> axi_hbm_port(29).aw.ready
		instHbm.io.AXI_29_WDATA    	<> axi_hbm_port(29).w.bits.data
		instHbm.io.AXI_29_WLAST    	<> axi_hbm_port(29).w.bits.last
		instHbm.io.AXI_29_WSTRB    	<> axi_hbm_port(29).w.bits.strb
		instHbm.io.AXI_29_WVALID   	<> axi_hbm_port(29).w.valid
		instHbm.io.AXI_29_WREADY   	<> axi_hbm_port(29).w.ready
		instHbm.io.AXI_29_RDATA    	<> axi_hbm_port(29).r.bits.data
		instHbm.io.AXI_29_RID      	<> axi_hbm_port(29).r.bits.id
		instHbm.io.AXI_29_RLAST    	<> axi_hbm_port(29).r.bits.last
		instHbm.io.AXI_29_RRESP    	<> axi_hbm_port(29).r.bits.resp
		instHbm.io.AXI_29_RVALID   	<> axi_hbm_port(29).r.valid
		instHbm.io.AXI_29_RREADY   	<> axi_hbm_port(29).r.ready
		instHbm.io.AXI_29_BID      	<> axi_hbm_port(29).b.bits.id
		instHbm.io.AXI_29_BRESP    	<> axi_hbm_port(29).b.bits.resp
		instHbm.io.AXI_29_BVALID   	<> axi_hbm_port(29).b.valid
		instHbm.io.AXI_29_BREADY   	<> axi_hbm_port(29).b.ready
		instHbm.io.AXI_29_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_29_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_30_ACLK		<> axiAclk
		instHbm.io.AXI_30_ARESET_N	<> axiLocked
		instHbm.io.AXI_30_ARADDR   	<> axi_hbm_port(30).ar.bits.addr
		instHbm.io.AXI_30_ARBURST  	<> axi_hbm_port(30).ar.bits.burst
		instHbm.io.AXI_30_ARID     	<> axi_hbm_port(30).ar.bits.id
		instHbm.io.AXI_30_ARLEN    	<> axi_hbm_port(30).ar.bits.len
		instHbm.io.AXI_30_ARSIZE   	<> axi_hbm_port(30).ar.bits.size
		instHbm.io.AXI_30_ARVALID  	<> axi_hbm_port(30).ar.valid
		instHbm.io.AXI_30_ARREADY  	<> axi_hbm_port(30).ar.ready
		instHbm.io.AXI_30_AWADDR   	<> axi_hbm_port(30).aw.bits.addr
		instHbm.io.AXI_30_AWBURST  	<> axi_hbm_port(30).aw.bits.burst
		instHbm.io.AXI_30_AWID     	<> axi_hbm_port(30).aw.bits.id
		instHbm.io.AXI_30_AWLEN    	<> axi_hbm_port(30).aw.bits.len
		instHbm.io.AXI_30_AWSIZE   	<> axi_hbm_port(30).aw.bits.size
		instHbm.io.AXI_30_AWVALID  	<> axi_hbm_port(30).aw.valid
		instHbm.io.AXI_30_AWREADY  	<> axi_hbm_port(30).aw.ready
		instHbm.io.AXI_30_WDATA    	<> axi_hbm_port(30).w.bits.data
		instHbm.io.AXI_30_WLAST    	<> axi_hbm_port(30).w.bits.last
		instHbm.io.AXI_30_WSTRB    	<> axi_hbm_port(30).w.bits.strb
		instHbm.io.AXI_30_WVALID   	<> axi_hbm_port(30).w.valid
		instHbm.io.AXI_30_WREADY   	<> axi_hbm_port(30).w.ready
		instHbm.io.AXI_30_RDATA    	<> axi_hbm_port(30).r.bits.data
		instHbm.io.AXI_30_RID      	<> axi_hbm_port(30).r.bits.id
		instHbm.io.AXI_30_RLAST    	<> axi_hbm_port(30).r.bits.last
		instHbm.io.AXI_30_RRESP    	<> axi_hbm_port(30).r.bits.resp
		instHbm.io.AXI_30_RVALID   	<> axi_hbm_port(30).r.valid
		instHbm.io.AXI_30_RREADY   	<> axi_hbm_port(30).r.ready
		instHbm.io.AXI_30_BID      	<> axi_hbm_port(30).b.bits.id
		instHbm.io.AXI_30_BRESP    	<> axi_hbm_port(30).b.bits.resp
		instHbm.io.AXI_30_BVALID   	<> axi_hbm_port(30).b.valid
		instHbm.io.AXI_30_BREADY   	<> axi_hbm_port(30).b.ready
		instHbm.io.AXI_30_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_30_RDATA_PARITY	<> DontCare

		instHbm.io.AXI_31_ACLK		<> axiAclk
		instHbm.io.AXI_31_ARESET_N	<> axiLocked
		instHbm.io.AXI_31_ARADDR   	<> axi_hbm_port(31).ar.bits.addr
		instHbm.io.AXI_31_ARBURST  	<> axi_hbm_port(31).ar.bits.burst
		instHbm.io.AXI_31_ARID     	<> axi_hbm_port(31).ar.bits.id
		instHbm.io.AXI_31_ARLEN    	<> axi_hbm_port(31).ar.bits.len
		instHbm.io.AXI_31_ARSIZE   	<> axi_hbm_port(31).ar.bits.size
		instHbm.io.AXI_31_ARVALID  	<> axi_hbm_port(31).ar.valid
		instHbm.io.AXI_31_ARREADY  	<> axi_hbm_port(31).ar.ready
		instHbm.io.AXI_31_AWADDR   	<> axi_hbm_port(31).aw.bits.addr
		instHbm.io.AXI_31_AWBURST  	<> axi_hbm_port(31).aw.bits.burst
		instHbm.io.AXI_31_AWID     	<> axi_hbm_port(31).aw.bits.id
		instHbm.io.AXI_31_AWLEN    	<> axi_hbm_port(31).aw.bits.len
		instHbm.io.AXI_31_AWSIZE   	<> axi_hbm_port(31).aw.bits.size
		instHbm.io.AXI_31_AWVALID  	<> axi_hbm_port(31).aw.valid
		instHbm.io.AXI_31_AWREADY  	<> axi_hbm_port(31).aw.ready
		instHbm.io.AXI_31_WDATA    	<> axi_hbm_port(31).w.bits.data
		instHbm.io.AXI_31_WLAST    	<> axi_hbm_port(31).w.bits.last
		instHbm.io.AXI_31_WSTRB    	<> axi_hbm_port(31).w.bits.strb
		instHbm.io.AXI_31_WVALID   	<> axi_hbm_port(31).w.valid
		instHbm.io.AXI_31_WREADY   	<> axi_hbm_port(31).w.ready
		instHbm.io.AXI_31_RDATA    	<> axi_hbm_port(31).r.bits.data
		instHbm.io.AXI_31_RID      	<> axi_hbm_port(31).r.bits.id
		instHbm.io.AXI_31_RLAST    	<> axi_hbm_port(31).r.bits.last
		instHbm.io.AXI_31_RRESP    	<> axi_hbm_port(31).r.bits.resp
		instHbm.io.AXI_31_RVALID   	<> axi_hbm_port(31).r.valid
		instHbm.io.AXI_31_RREADY   	<> axi_hbm_port(31).r.ready
		instHbm.io.AXI_31_BID      	<> axi_hbm_port(31).b.bits.id
		instHbm.io.AXI_31_BRESP    	<> axi_hbm_port(31).b.bits.resp
		instHbm.io.AXI_31_BVALID   	<> axi_hbm_port(31).b.valid
		instHbm.io.AXI_31_BREADY   	<> axi_hbm_port(31).b.ready
		instHbm.io.AXI_31_WDATA_PARITY	<> 0.U
		instHbm.io.AXI_31_RDATA_PARITY	<> DontCare
	}
	hbmInit2(instHbm, axi_hbm_port, axiAclk, axiLocked)

	// APB channels
	instHbm.io.APB_0_PWDATA    <> 0.U
	instHbm.io.APB_0_PADDR     <> 0.U
	instHbm.io.APB_0_PCLK      <> apb0Pclk
	instHbm.io.APB_0_PENABLE   <> 0.U
	instHbm.io.APB_0_PRESET_N  <> glblLocked
	instHbm.io.APB_0_PSEL      <> 0.U
	instHbm.io.APB_0_PWRITE    <> 0.U
	instHbm.io.APB_0_PRDATA    <> DontCare
	instHbm.io.APB_0_PREADY    <> DontCare
	instHbm.io.APB_0_PSLVERR   <> DontCare

	instHbm.io.APB_1_PWDATA    <> 0.U
	instHbm.io.APB_1_PADDR     <> 0.U
	instHbm.io.APB_1_PCLK      <> apb1Pclk
	instHbm.io.APB_1_PENABLE   <> 0.U
	instHbm.io.APB_1_PRESET_N  <> glblLocked
	instHbm.io.APB_1_PSEL      <> 0.U
	instHbm.io.APB_1_PWRITE    <> 0.U
	instHbm.io.APB_1_PRDATA    <> DontCare
	instHbm.io.APB_1_PREADY    <> DontCare
	instHbm.io.APB_1_PSLVERR   <> DontCare

	instHbm.io.apb_complete_0	<> DontCare
	instHbm.io.apb_complete_1	<> DontCare

	// Stats
	instHbm.io.DRAM_0_STAT_TEMP	<> DontCare
	instHbm.io.DRAM_1_STAT_TEMP	<> DontCare
	instHbm.io.DRAM_0_STAT_CATTRIP	<> DontCare
	instHbm.io.DRAM_1_STAT_CATTRIP	<> DontCare

	// AXI User bits
    axi_hbm_port(0).r.bits.user := DontCare
	axi_hbm_port(0).b.bits.user := DontCare
    axi_hbm_port(1).r.bits.user := DontCare
	axi_hbm_port(1).b.bits.user := DontCare
    axi_hbm_port(2).r.bits.user := DontCare
	axi_hbm_port(2).b.bits.user := DontCare
    axi_hbm_port(3).r.bits.user := DontCare
	axi_hbm_port(3).b.bits.user := DontCare
    axi_hbm_port(4).r.bits.user := DontCare
	axi_hbm_port(4).b.bits.user := DontCare
    axi_hbm_port(5).r.bits.user := DontCare
	axi_hbm_port(5).b.bits.user := DontCare
    axi_hbm_port(6).r.bits.user := DontCare
	axi_hbm_port(6).b.bits.user := DontCare
    axi_hbm_port(7).r.bits.user := DontCare
	axi_hbm_port(7).b.bits.user := DontCare
    axi_hbm_port(8).r.bits.user := DontCare
	axi_hbm_port(8).b.bits.user := DontCare
    axi_hbm_port(9).r.bits.user := DontCare
	axi_hbm_port(9).b.bits.user := DontCare
    axi_hbm_port(10).r.bits.user := DontCare
	axi_hbm_port(10).b.bits.user := DontCare
    axi_hbm_port(11).r.bits.user := DontCare
	axi_hbm_port(11).b.bits.user := DontCare
    axi_hbm_port(12).r.bits.user := DontCare
	axi_hbm_port(12).b.bits.user := DontCare
    axi_hbm_port(13).r.bits.user := DontCare
	axi_hbm_port(13).b.bits.user := DontCare
    axi_hbm_port(14).r.bits.user := DontCare
	axi_hbm_port(14).b.bits.user := DontCare
    axi_hbm_port(15).r.bits.user := DontCare
	axi_hbm_port(15).b.bits.user := DontCare
    axi_hbm_port(16).r.bits.user := DontCare
	axi_hbm_port(16).b.bits.user := DontCare
    axi_hbm_port(17).r.bits.user := DontCare
	axi_hbm_port(17).b.bits.user := DontCare
    axi_hbm_port(18).r.bits.user := DontCare
	axi_hbm_port(18).b.bits.user := DontCare
    axi_hbm_port(19).r.bits.user := DontCare
	axi_hbm_port(19).b.bits.user := DontCare
    axi_hbm_port(20).r.bits.user := DontCare
	axi_hbm_port(20).b.bits.user := DontCare
    axi_hbm_port(21).r.bits.user := DontCare
	axi_hbm_port(21).b.bits.user := DontCare
    axi_hbm_port(22).r.bits.user := DontCare
	axi_hbm_port(22).b.bits.user := DontCare
    axi_hbm_port(23).r.bits.user := DontCare
	axi_hbm_port(23).b.bits.user := DontCare
    axi_hbm_port(24).r.bits.user := DontCare
	axi_hbm_port(24).b.bits.user := DontCare
    axi_hbm_port(25).r.bits.user := DontCare
	axi_hbm_port(25).b.bits.user := DontCare
    axi_hbm_port(26).r.bits.user := DontCare
	axi_hbm_port(26).b.bits.user := DontCare
    axi_hbm_port(27).r.bits.user := DontCare
	axi_hbm_port(27).b.bits.user := DontCare
    axi_hbm_port(28).r.bits.user := DontCare
	axi_hbm_port(28).b.bits.user := DontCare
    axi_hbm_port(29).r.bits.user := DontCare
	axi_hbm_port(29).b.bits.user := DontCare
    axi_hbm_port(30).r.bits.user := DontCare
	axi_hbm_port(30).b.bits.user := DontCare
    axi_hbm_port(31).r.bits.user := DontCare
	axi_hbm_port(31).b.bits.user := DontCare
}
